Sub-Rate Bang-Bang Phase Detector Using Multiphase Clock Sampling
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Solution Overview
Problem
Bang-bang phase detectors in phase locked loops require a high-speed clock, which is inconvenient and power-intensive, especially for high data rates, necessitating a solution for a simple phase detector that can operate with a reduced frequency reference clock.
Innovation Solution
A sub-rate bang-bang phase detector design using edge-triggered flip-flops or transparent latches to sample an input data stream with a reference clock and phase-shifted clocks, generating logic signals indicative of phase transitions, allowing for frequency adjustments with a reduced frequency reference clock, implemented in a phase locked loop with a multiphase voltage-controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed clock is used in a bang-bang phase detector, then phase transition detection accuracy is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent divides the sampling process into multiple phases by using phase-shifted clocks (e.g., 0°, 90°, 180°, 270°) instead of a single high-speed clock. Each phase samples different portions of the data stream, allowing accurate phase detection at a lower overall clock frequency. This segmentation of the sampling function across multiple lower-frequency clock phases reduces power consumption while maintaining detection accuracy.
Solution Approach 2:
The patent employs periodic sampling at reduced clock rates by cycling through multiple phase-shifted clock signals. Instead of continuous high-speed sampling, the system performs periodic sampling at each phase level, accumulating phase information over complete cycles. This periodic action at lower frequencies achieves the same detection accuracy with significantly reduced power consumption compared to continuous high-speed operation.
2Measurement precision
If a high-speed clock is used in a bang-bang phase detector, then phase transition detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the high-speed sampling function into multiple lower-speed sampling operations using phase-shifted clocks. Each clock phase handles a portion of the sampling task, allowing the use of simpler, lower-frequency logic elements. This segmentation reduces device complexity by replacing complex high-speed logic with multiple simpler low-speed logic blocks operating in coordination.
Solution Approach 2:
The patent introduces phase-shifted clock signals as intermediaries between the data stream and the sampling logic. These intermediate clock signals at reduced frequencies mediate the sampling process, allowing accurate phase detection without requiring complex high-speed logic. The phase-shifted clocks act as mediators that translate the high-speed sampling requirement into multiple manageable low-speed operations.
3Use of energy by moving object
If a reduced frequency reference clock is used, then power consumption is reduced and device complexity is reduced, but phase transition detection capability deteriorates
Solution Approach 1:
The patent uses periodic sampling at multiple phase levels with reduced frequency clocks to achieve complete phase detection coverage. By cycling through 0°, 90°, 180°, and 270° phases in sequence, the system periodically samples all critical points of the data stream. This periodic multi-phase sampling maintains detection capability despite using lower-frequency clocks, as each phase contributes information about a different portion of the signal cycle.
Solution Approach 2:
The patent changes the parameter of clock frequency from a single high value to multiple lower values with different phase offsets. Instead of using one high-frequency clock, the system employs multiple lower-frequency clocks with varying phase parameters (0°, 90°, 180°, 270°). This parameter transformation allows the system to maintain detection accuracy by exploiting the phase dimension, compensating for the reduced frequency through increased phase diversity.
Data Source
AI summary
The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.