Sub-Sampling PLL Circuit for Low Phase Noise Clock Locking
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) suffer from increased phase noise due to noise multiplication in the feedback path, and sub-sampling PLLs face errors in clock sampling when applied to delay-locked loops, leading to performance limitations.
Innovation Solution
A phase-locked loop circuit utilizing two sub-sampling phase detectors with a symmetric circuit architecture and charge pumps to achieve symmetric sampling, ensuring accurate clock sampling and reduced phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL with N-divider feedback path is used, then frequency synchronization is achieved, but phase noise is multiplied by N2 leading to degraded performance
Solution Approach 1:
The patent removes the N-divider from the feedback path of the PLL circuit. By extracting this noise-amplifying component, the feedback path directly connects the VCO output to the phase detector, preventing noise multiplication by N2 while maintaining frequency synchronization through the charge pump and filter mechanism
Solution Approach 2:
The patent implements a feedback mechanism using the charge pump and low-pass filter to maintain phase lock. The phase detector compares the reference clock with the VCO output, and the charge pump generates correction signals that are filtered and fed back to adjust the VCO frequency, achieving synchronization without the noisy N-divider
2Object-affected harmful factors
If sub-sampling phase detector is used to avoid noise multiplication, then phase noise is reduced, but sampling position errors occur due to asymmetric loads in delay-locked loop application
Solution Approach 1:
The patent introduces asymmetry compensation by adding different load capacitances (C1 and C2) to the two sub-sampling phase detectors. This deliberate asymmetric design counteracts the inherent load differences in the delay-locked loop circuit, balancing the sampling positions and eliminating errors caused by asymmetric loading
Solution Approach 2:
The patent modifies the load parameters of the sub-sampling phase detectors by adding external capacitances C1 and C2. By changing these electrical parameters, the sampling characteristics of each detector are adjusted to achieve symmetric sampling positions despite the asymmetric circuit topology
Data Source
AI summary
A phase-locked loop circuit includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay phase-locked loop phase locks a first reference clock and a second reference clock to an input clock, and includes a phase correction circuit, an integrator, a first sub-sampling phase detector, and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output clock with a predetermined phase-locked loop frequency, and the output clock is phase-locked to the first reference clock, the sub-sampling phase-locked loop includes a second sub-sampling phase detector, a second charge pump, a phase frequency detecting circuit, a voltage controlled oscillator and a first frequency divider. The first sub-sampling phase detector and the second sub-sampling phase detector have a symmetric circuit structure, and a first charge pump circuit and a second charge pump circuit have a symmetric circuit structure.