Sub-VDD Bitline Precharge SRAM Circuit for Stability

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Solution Overview

Problem

Conventional SRAM designs face challenges in scalability and stability due to competing requirements of read and write margins, with precharging bitlines to sub-VDD levels improving stability but at the cost of cycle time and with limited control over discharge levels, and PVT variations affecting precharge voltage.

Innovation Solution

A diode-connected PFET device is used as a body-contacted bitline precharge device to create a sub-VDD precharge level, self-compensating for PVT variations and level-shifting the sense-amp voltage to full VDD, reducing cycle time pushouts and improving stability margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If bitlines are precharged to full VDD level, then read operation speed is improved, but cell stability margin deteriorates due to charge injection causing data corruption

Engineering Contradiction:

Improveread operation speedVSAvoidcell stability margin

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent changes the precharge voltage parameter from full VDD to a controlled sub-VDD level (VBLPRE), reducing charge injection into the cell while maintaining adequate signal levels for read operations. This is achieved through a dedicated precharge circuit that sets BLPRE to an optimized voltage level between GND and VDD.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If bitlines are precharged to sub-VDD level using pulse method, then cell stability margin is improved, but cycle time increases due to timing constraints

Engineering Contradiction:

Improvestability marginVSAvoidcycle time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs bitline precharging to sub-VDD level as a preliminary action before the read operation begins. The precharge circuit activates early to establish the optimal voltage level on bitlines, ensuring cell stability is achieved without requiring additional timing adjustments or extending the overall cycle time.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If NFET source follower is used for sub-VDD precharge, then precharge level control is simplified, but conduction range is limited and slew rate increases

Engineering Contradiction:

Improveprecharge level controlVSAvoidprecharge speed

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The patent replaces the NFET source follower mechanism with a PFET-based precharge circuit that uses body bias control to regulate the precharge voltage. This substitution eliminates the limited conduction range and high slew rate issues of the source follower by using the PFET's superior voltage handling capabilities and body effect for precise voltage control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If externally controlled precharge voltage is used, then precharge level adaptability is improved, but PVT variations cause large precharge level shifts

Engineering Contradiction:

Improveprecharge level adaptabilityVSAvoidprecharge level stability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent incorporates body bias feedback control where the body of the PFET precharge device is connected to a bias network that senses and compensates for PVT variations. This feedback mechanism automatically adjusts the body bias voltage to maintain a stable precharge level despite changes in process, voltage, or temperature conditions.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS8279687B2Single supply sub VDD bit-line precharge SRAM and method for level shifting

Publication Date: 2012.10.02 MARVELL ASIA PTE LTD

AI summary

A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.