Sub-vector instructions for scalable vector architecture

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Solution Overview

Problem

The adoption of scalable vector instruction sets is hindered by the need to redevelop legacy code optimized for non-scalable vector architectures, which rely on known vector lengths for performance optimizations.

Innovation Solution

The introduction of sub-vector-supporting instructions within the scalable vector instruction set architecture allows for treating vectors as composed of sub-vectors of known length, enabling easier mapping of non-scalable code to scalable code and retaining performance optimizations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If scalable vector instruction set architecture is adopted, then hardware flexibility and performance are improved, but software development effort increases due to need to redevelopment legacy code

Engineering Contradiction:

Improvehardware performanceVSAvoidsoftware development effort

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent segments vectors into sub-vectors with fixed, known lengths. This segmentation allows legacy code optimized for non-scalable architectures to be mapped to scalable architectures by treating each sub-vector as a manageable unit with predictable behavior, thereby reducing software development effort while maintaining hardware flexibility

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces sub-vector length as a new parameter that is known at compile time, contrasting with the unknown vector length in scalable architectures. This parameter change enables performance optimizations in software while the hardware can still operate with flexible, scalable vector lengths, resolving the contradiction between hardware performance and software development effort

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If non-scalable vector architecture is used, then software optimization is easier with known vector lengths, but hardware flexibility and performance are limited

Engineering Contradiction:

Improvesoftware optimization easeVSAvoidhardware flexibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent adds a new dimension to the vector architecture by introducing sub-vectors within vectors. This creates a hierarchical structure where the inner dimension (sub-vector length) is fixed and known for software optimization, while the outer dimension (total vector length) remains scalable and flexible for hardware adaptation

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250156184A1Sub-vector-supporting instruction for scalable vector instruction set architecture

Publication Date: 2025.05.15 ARM LTD

AI summary

An apparatus has processing circuitry (16) to perform data processing, and instruction decoding circuitry (10) to control the processing circuitry to perform the data processing in response to decoding of program instructions defined according to a scalable vector instruction set architecture supporting vector instructions operating on vectors of scalable vector length to enable the same instruction sequence to be executed on apparatuses with hardware supporting different maximum vector lengths. The instruction decoding circuitry and the processing circuitry support a sub-vector-supporting instruction which treats a given vector as comprising a plurality of sub-vectors with each sub-vector comprising a plurality of vector elements. In response to the sub-vector-supporting instruction, the instruction decoding circuitry controls the processing circuitry to perform an operation for the given vector at sub-vector granularity. Each sub-vector has an equal sub-vector length.