Sub Volt Flash Memory Bulk Voltage Control
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Solution Overview
Problem
Reducing power consumption and achieving faster semiconductor circuits while maintaining sufficient margins for circuit elements, which is challenging at sub-volt operating levels.
Innovation Solution
The system employs MOS transistors with a bulk voltage terminal that can be set differently for each transistor, either to the supply voltage or ground, to forward or reverse bias pn junctions, allowing for selective bulk voltage settings in comparators, operational amplifiers, and other circuits within a memory system, enabling bipolar action and optimizing voltage and current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating voltage is reduced to lower power consumption, then power consumption decreases, but circuit speed and signal margins deteriorate
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bulk voltage of MOS transistors independently from the supply voltage. By changing the bulk voltage parameter to be different from the supply voltage (e.g., using a separate bulk voltage generator), the system can optimize transistor characteristics for speed while operating at reduced supply voltages for low power consumption.
Solution Approach 2:
The patent implements dynamics by making the bulk voltage adjustable and selective rather than fixed. Different bulk voltages can be applied to different transistors based on their specific operational requirements, allowing the system to adapt transistor behavior dynamically to balance between speed and power consumption.
2Use of energy by moving object
If operating voltage is reduced to lower power consumption, then power consumption decreases, but noise margins and signal margins deteriorate
Solution Approach 1:
The patent uses parameter changes to adjust the bulk voltage separately from the supply voltage, allowing optimization of transistor threshold voltages and noise margins independent of the reduced supply voltage. This enables maintaining adequate noise margins even at lower operating voltages.
Solution Approach 2:
The patent applies local quality by allowing different bulk voltages to be applied to different transistors or transistor groups based on their specific noise margin requirements. This localized optimization ensures that critical circuits maintaining adequate noise margins while others can operate at lower voltages for reduced power consumption.
3Reliability
If bulk voltage is set to forward bias pn junctions, then latch-up conditions are prevented, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary bulk voltage control mechanism that mediates between the supply voltage and the pn junction biasing requirements. By using a separate bulk voltage generator or control circuitry, the system can prevent latch-up conditions through proper junction biasing without directly complicating the main signal processing paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, minimizes noise, and prevents latch-up conditions, thereby enhancing the performance and reliability of memory systems operating at sub-volt levels.
Implementation Method 1
The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor
Implementation Method 2
the dimensions of the MOS transistors and the voltages applied thereto may provide bipolar action in the MOS transistors
Data Source
AI summary
Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.