Sub Word Line Driver Keeper Transistor Sharing
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Solution Overview
Problem
The increasing integration density of semiconductor memory devices requires a reduction in the area occupied by sub word line drivers, as they currently include CMOS inverters and keeper transistors that occupy significant space, making it challenging to control sub word lines efficiently.
Innovation Solution
The sub word line driver is reconfigured to eliminate the keeper transistor by rearranging sub word lines so that adjacent lines are controlled by main word lines with different logic levels, allowing for shared keeper transistors between adjacent drivers, thereby reducing the overall area required for the driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sub word line driver includes CMOS inverter and keeper transistor composed of NMOS transistors, then the sub word line driver can control sub word lines effectively, but the sub word line driver requires two wells disposed to be spaced apart from each other, occupying significant area
Solution Approach 1:
The patent merges the first and second wells into a single shared well structure. The first NMOS transistor (first keeper transistor) and second NMOS transistor (second keeper transistor) are both formed in the same well, eliminating the need for two separately disposed wells. This merging reduces the total area occupied by the sub word line driver while maintaining the functionality of both keeper transistors for controlling adjacent sub word lines.
2Productivity
If the integration density of memory cell array is decreased, then the area of control circuit region is decreased, but it becomes more challenging to accommodate the sub word line driver with its required well structures
Solution Approach 1:
By combining the well structures for the first and second keeper transistors into a single shared well, the patent significantly reduces the area required for the sub word line driver. This area reduction directly supports higher integration density in the memory device, allowing more memory cells to be packed into the same chip area while maintaining adequate space for control circuitry.
Solution Approach 2:
The shared well structure serves multiple functions: it houses both the first NMOS transistor (first keeper transistor) and the second NMOS transistor (second keeper transistor), which respectively control different sub word lines. This multi-functional use of a single well structure maximizes the utility of the limited control circuit region area.
Data Source
AI summary
A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.