Sub Word Line Driving Circuit Encoding for Memory Routing
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Solution Overview
Problem
As semiconductor memory devices, such as DRAM, increase in density, the complexity of routing wiring lines for sub word line driving signals increases, leading to reduced routing degree of freedom and increased wiring complexity, which complicates the design and operation of sub word line driving circuits.
Innovation Solution
A memory device that generates encoded sub word line driving signals based on main word line driving signals, allowing the sub word line driving signals to be output in different orders depending on whether an odd or even main word line is activated, thereby reducing wiring complexity and increasing routing freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of the DRAM increases, then the memory capacity increases, but the complexity of routing wiring lines increases
Solution Approach 1:
The patent segments the sub word line driving signals into multiple groups (first group and second group) that can be independently controlled. This segmentation allows different routing paths to be used for different signal groups, reducing the overall complexity of the routing wiring lines while maintaining high memory capacity.
Solution Approach 2:
The patent introduces a new dimension of control by using an odd/even signal to selectively activate different sub word line drivers. This dimensional approach allows the same physical wiring infrastructure to serve multiple logical functions, reducing routing complexity without sacrificing memory density.
2Quantity of substance
If the complexity of the routing wiring line increases, then the memory density can be maintained, but the distance between wiring lines increases
Solution Approach 1:
By dividing sub word line driving signals into multiple groups that can be routed through different paths, the patent reduces the distance between wiring lines. Each segmented group can be transmitted over shorter distances through optimized local routing, maintaining memory density while reducing wire length.
3Device complexity
If the routing degree of freedom is reduced, then the wiring complexity decreases, but the adaptability of the sub word line driving circuit decreases
Solution Approach 1:
The patent implements dynamic adaptability by using control signals (odd/even signals, first/second control signals) that allow the sub word line driving circuit to flexibly select between different routing configurations. This dynamic control maintains low wiring complexity while preserving full adaptability to different memory access patterns.
Solution Approach 2:
The patent introduces control signals as intermediaries that mediate between the memory control logic and the sub word line drivers. These intermediary signals enable the circuit to adapt to different operating conditions without requiring complex direct routing, thus maintaining simplicity while enhancing versatility.
Data Source
AI summary
A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.