Sub-word Line Control Signal Generator Layout for DRAM

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges with high power consumption and noise due to long sub-word line control signal supply lines, which also result in slower enable speeds and increased area size, especially as DRAM becomes more integrated and larger in capacity.

Innovation Solution

The layout structure of a sub-word line control signal generator is optimized by placing at least two generators at the edge areas of the memory cell array to directly supply the sub-word line control signal to the sub-word line driver without the need for amplifiers or repeaters, reducing the length and load of supply lines and minimizing VPP power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the sub-word line control signal supply line is extended to cover a large area, then the signal can reach more memory blocks, but the power consumption and noise increase

Engineering Contradiction:
Improvecoverage area of signal supplyVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

The patent divides the memory block arrangement into alternating patterns (first memory blocks and second memory blocks) with different sub-word line control signal supply configurations. This segmentation allows the signal supply to be concentrated in specific areas rather than uniformly distributed, reducing overall power consumption while maintaining adequate coverage through the alternating pattern.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different sub-word line control signal supply line configurations to different locations (first memory blocks vs. second memory blocks). By tailoring the signal supply characteristics to specific local areas, the design optimizes power consumption in each region while ensuring adequate signal distribution across the entire memory array.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the sub-word line control signal supply line is extended to cover a large area, then the signal can reach more memory blocks, but the noise increases

Engineering Contradiction:
Improvecoverage area of signal supplyVSAvoidnoise
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The alternating pattern of first and second memory blocks creates segmented signal supply zones. This segmentation limits the continuous extent of signal supply lines, thereby reducing the cumulative noise generated along the signal path while still providing adequate coverage through the distributed alternating configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different noise management strategies are applied to different memory block types. By configuring signal supply lines differently for first versus second memory blocks, the design locally optimizes noise characteristics in each region, preventing noise accumulation across the entire array.

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If the sub-word line control signal supply line length is increased, then more memory blocks can be accessed, but the enable speed decreases

Engineering Contradiction:
Improvecoverage area of signal supplyVSAvoidenable speed of sub-word line
Core Design Contradiction:
Area of stationary objectVSSpeed

Solution Approach 1:

The alternating configuration of first and second memory blocks creates a segmented signal distribution network. This segmentation ensures that no single signal path becomes excessively long, as the pattern repeats periodically. Consequently, the maximum signal path length is limited, preserving enable speed while expanding overall coverage through the repeated alternating pattern.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends signal coverage not by lengthening individual supply lines in one dimension, but by adding spatial distribution across multiple alternating memory block patterns. This dimensional approach to expansion maintains signal path lengths within acceptable limits while achieving broader coverage through the alternating configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8203904B2Semiconductor memory device and layout structure of sub-word line control signal generator
Publication Date: 2012.06.19 SAMSUNG ELECTRONICS CO LTD
  • US8203904B2 patent drawing
  • US8203904B2 patent drawing
  • US8203904B2 patent drawing

AI summary

A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.