Sub Wordline Driver Layout for DRAM Speed and Reliability
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Solution Overview
Problem
As memory devices, such as DRAMs, are miniaturized, the increasing number of memory cells connected to each wordline and decreasing spacing between wordlines lead to speed delays, necessitating the use of sub wordline drivers to manage wordline voltage effectively, but this poses challenges in securing operational reliability due to layout constraints.
Innovation Solution
The layout of sub wordline drivers is redesigned to reduce the gap between direct contacts, with transistors and gate lines arranged in specific directions to improve operational reliability, allowing for efficient wordline management and reduced unnecessary space, thereby enhancing the sub wordline driver's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of memory cells connected to one wordline is increased to improve integration density, then the area utilization is improved, but the speed delay increases due to larger capacitance loading
Solution Approach 1:
The patent divides the wordline driver function into multiple sub-wordline drivers (SWD1, SWD2, etc.), each responsible for driving a specific wordline. This segmentation allows each driver to manage only the capacitance of its assigned wordline, reducing the loading burden on each individual driver and maintaining fast switching speeds while supporting a larger total number of memory cells per wordline through increased integration density
2Area of stationary object
If the spacing between wordlines is decreased to increase memory cell density, then the area utilization is improved, but the operational reliability deteriorates due to layout constraints
Solution Approach 1:
The patent positions sub-wordline drivers in different spatial locations (e.g., SWD1 above SWD2 in the second direction perpendicular to wordline extension) and uses direct contacts extending in the second direction to connect transistors to wordlines. This dimensional arrangement allows compact layout with reduced gaps between direct contacts while maintaining proper electrical connections and operational reliability through optimized signal paths
3Speed
If sub wordline drivers are introduced to reduce speed delay, then the driving speed is improved, but the device complexity increases due to additional components
Solution Approach 1:
The patent merges the sub-wordline drivers into the existing memory device architecture, with each SWD integrated alongside its corresponding wordline and memory cells. The direct contacts are shared between adjacent sub-wordline drivers (e.g., the second direct contact of SWD1 serves both SWD1 and SWD2), reducing redundant components and simplifying the overall device structure while maintaining the speed benefits of segmented driving
Data Source
AI summary
A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.