Sub-wordline Driver Segmentation for Semiconductor Delay
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Solution Overview
Problem
As semiconductor memory devices increase in capacity and size, the resistance of word lines in memory cells leads to increased delay times, necessitating a reduction in word line length and the use of hierarchical word-line driving methods to divide word lines into sub-wordlines, but existing solutions struggle to minimize the area occupied by sub-wordline drivers while efficiently driving multiple sub-wordlines.
Innovation Solution
A sub-wordline driver is designed with a selection controller and driving circuits that selectively output sub-wordline drive signals in response to main wordline drive signals and wordline selection signals, allowing for the division of sub-wordlines into shorter segments and minimizing the driver's area by classifying wordline selection signals into groups and reducing the number of main wordline drive signals, thereby optimizing the layout and reducing line width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If word lines are divided into sub-wordlines to reduce resistance and delay time, then the driving capability is improved, but the area occupied by sub-wordline drivers increases
Solution Approach 1:
The patent divides word lines into multiple sub-wordlines (first sub-wordlines and second sub-wordlines) that are driven by separate driving circuits. This segmentation allows each driver to control fewer lines, reducing the area required per driver while collectively covering the entire word line array, thus resolving the contradiction between improved driving capability and increased total driver area.
Solution Approach 2:
The patent introduces a hierarchical control structure with main wordline drive signals and group-specific wordline selection signals. This multi-dimensional signaling approach enables compact driver design by organizing control signals in groups, allowing the driver area to scale more efficiently with increased memory capacity while maintaining low delay times.
2Quantity of substance
If the number of sub-wordlines is increased to handle higher memory capacity, then the memory capacity is improved, but the complexity of the driver circuit increases
Solution Approach 1:
The driver circuit is segmented into multiple independent driving circuits, each responsible for a specific group of sub-wordlines. This modular segmentation allows the system to scale to higher memory capacities by simply adding more driving circuits without proportionally increasing the complexity of each individual circuit, as each circuit handles a limited, manageable subset of control signals.
Solution Approach 2:
Each driving circuit is designed with universal functionality to handle its assigned group of sub-wordlines using the same control mechanism (main wordline drive signal plus group-specific selection signal). This universality means that the same circuit design can be replicated multiple times to support increased memory capacity without increasing the complexity of the fundamental circuit architecture.
3Speed
If the length of word lines is reduced to lower resistance, then the delay time is reduced, but the memory cell area increases
Solution Approach 1:
By dividing the memory cell array into multiple blocks, each with its own sub-wordlines of optimized length, the patent achieves low resistance and delay time within each block while the total memory capacity is maintained across all blocks. The segmentation allows short local connections within blocks while the overall array layout preserves high density.
Data Source
AI summary
A sub-wordline driver for a semiconductor memory device includes a plurality of first active regions spaced apart from each other by a predetermined distance in each of a first direction and a second direction within a first region and a main wordline formed to traverse the plurality of first active regions by extending in the first direction. The main wordline includes a first line formed to extend in the first direction, a second line formed to extend in the first direction, and configured to be spaced apart from the first line by a predetermined distance in the second direction, and a connection line configured to interconnect the first line and the second line in the second direction at an end portion of the first region.