Sub-Wordline Error Mapping for Targeted Memory Cell Repair

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Solution Overview

Problem

Conventional volatile memory devices face challenges in efficiently detecting and repairing defects in sub-wordlines and sub-wordline driver blocks, leading to system errors and wastage of redundancy memory cells due to inadequate error counting and repair strategies.

Innovation Solution

A storage device with a storage controller that includes a structure map table to track error counts for each unit area, allowing precise detection of defective sub-wordlines and sub-wordline driver blocks, and performs targeted repairs using redundancy memory cells to minimize waste and prevent additional errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional error counting methods are used in volatile memory, then the detection process is simple, but the precision of defect detection is insufficient leading to inadequate identification of defective sub-wordlines and sub-wordline driver blocks

Engineering Contradiction:
Improvedefect detection precisionVSAvoiderror counting system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple sub-cell arrays, each with its own sub-wordline driver block. Error counting is performed separately for each sub-cell array and sub-wordline driver block, enabling precise identification of defective components without requiring complex system-wide analysis.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A structure map table is introduced as an intermediary data structure to store and manage error counts for different unit areas, sub-wordlines, and sub-wordline driver blocks. This table serves as a mediator between the error detection process and the repair decision-making process, organizing information in a manageable format.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If redundancy memory cells are used to repair defects, then the reliability of the memory device is improved, but the redundancy cells are wasted when defects are not precisely identified

Engineering Contradiction:
Improvememory device reliabilityVSAvoidredundancy cell waste
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The error counting and repair process is applied locally to specific sub-cell arrays and sub-wordline driver blocks rather than globally across the entire memory device. This localized approach ensures that redundancy cells are only used when and where actually needed, preventing waste while maintaining reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system continuously monitors error counts in each sub-cell array and sub-wordline driver block, providing feedback to determine when repair is necessary. This feedback mechanism ensures that redundancy cells are activated only when actual defects are detected, optimizing their utilization.

Inventive Principle:
Principle #23Feedback

3Reliability

If the entire memory device is repaired when defects occur, then system errors are prevented, but unnecessary repairs cause redundancy cell waste and reduced productivity

Engineering Contradiction:
Improvesystem error preventionVSAvoidrepair operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory device is segmented into independent sub-cell arrays and sub-wordline driver blocks, allowing repair operations to be performed on only the defective segments rather than the entire device. This segmentation enables selective repair, maintaining system reliability while improving repair efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing full memory device repair, the system applies partial repair actions only to the specific sub-cell arrays or sub-wordline driver blocks that have exceeded error thresholds. This partial action approach prevents unnecessary repairs while ensuring adequate protection against system errors.

Inventive Principle:
Principle #16Partial or excessive action

4Measurement precision

If detailed error counting for each unit area is implemented, then the precision of defect localization is improved, but the complexity of error management increases

Engineering Contradiction:
Improveerror localization precisionVSAvoiderror management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The memory device is divided into manageable sub-cell arrays, with each array further divided into unit areas. Error counting is performed at the unit area level within each sub-cell array, providing detailed error localization while keeping the management complexity manageable through hierarchical organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The structure map table serves as an intermediary that automatically manages the detailed error count data for each unit area, sub-wordline, and sub-wordline driver block. This intermediary structure simplifies the management complexity by providing a standardized format for storing and accessing detailed error information.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12456534B2Storage devices having enhanced error detection and memory cell repair
Publication Date: 2025.10.28 SAMSUNG ELECTRONICS CO LTD
  • US12456534B2 patent drawing
  • US12456534B2 patent drawing
  • US12456534B2 patent drawing

AI summary

A storage device includes a volatile memory and a storage controller, which is configured to control the volatile memory. The volatile memory includes a memory cell array, which has a plurality of sub-cell arrays therein, and a plurality of sub-wordline driver blocks, which are configured to drive sub-wordlines electrically connected to at least one of the plurality of sub-cell arrays. The storage controller includes: a volatile memory interface configured to transmit data to and receive data from the volatile memory, and detect an error bit(s) of data output from the volatile memory, a working memory configured to store a structure map table, which maps unit areas of the volatile memory, the sub-wordlines, and the plurality of sub-wordline driver blocks, and a processor, which is configured to: update an error count of a unit area of the volatile memory that corresponds to the error bit(s) detected from the volatile memory interface to the structure map table, detect at least one of a defective sub-wordline and defective sub-wordline driver block, by accessing the structure map table, and then repair at least one memory cell connected to the defective sub-wordline and/or repair at least one memory cell associated with the defective sub-wordline driver block.