In-Memory Subarray Data Movement Using On-Pitch Sensing Circuits
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Solution Overview
Problem
Data movement between and within banks of a processing-in-memory (PIM) device is inefficient, leading to increased processing time and power consumption, as existing systems require significant data transfer over buses and external processing resources that do not conform to memory array pitch rules.
Innovation Solution
The implementation of a memory device with sensing circuitry formed on pitch with memory cells, allowing data sensing and compute functions to be performed locally within the array, reducing the need for external data transfer and enabling simultaneous parallel operations across multiple subarrays using a shared I/O line data flow pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred over external buses between processing resources and memory arrays, then data access is enabled, but data movement speed and efficiency are limited
Solution Approach 1:
The patent merges the processing resources and memory array into a single integrated device, eliminating the need for external buses. The processing circuitry is directly coupled to the memory array within the same device, allowing data to be processed in-place without external data transfer, thereby achieving up to 64-fold improvement in data movement speed while reducing interface complexity
Solution Approach 2:
The patent introduces an intermediary data movement mechanism within the integrated device that enables direct data transfer between memory arrays and processing circuitry without external bus interfaces. This internal data path acts as an intermediary that bypasses the limitations of external bus architectures
2Power
If external processing resources are used to process data from memory arrays, then computational tasks can be performed, but power consumption increases due to data transfer
Solution Approach 1:
The patent implements self-service processing where the integrated device processes data internally without requiring external processing resources. The processing circuitry within the device performs computational tasks directly on data stored in the memory array, eliminating the energy-consuming data transfer to and from external processors while maintaining high computational throughput
Solution Approach 2:
By merging processing and memory functions into a single device, the patent eliminates the energy overhead of external data transfer while preserving computational capability. The integrated architecture allows data to remain in the memory array during processing, significantly reducing power consumption compared to external processing architectures
3Productivity
If data is moved between banks within a processing-in-memory device, then parallel processing is enabled, but data movement efficiency is reduced
Solution Approach 1:
The patent segments the memory array into multiple banks, each capable of independent parallel processing operations. This segmentation enables simultaneous data processing across multiple banks without requiring inefficient data movement between them, as each bank can operate autonomously with its own processing circuitry, thereby maintaining high productivity while eliminating data movement delays
Solution Approach 2:
The patent merges processing circuitry with each memory bank to create independently functional units. This merging allows each bank to perform parallel processing operations on its local data without transferring data to other banks, eliminating inter-bank data movement time while preserving parallel processing capabilities
Data Source
AI summary
The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.