Sub-Array Memory Layout for Low-Latency Meta Data ECC
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently storing and managing meta data, leading to increased latency due to the need for generating parity data, especially with the scaling down of manufacturing processes and increased memory capacity.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with sub-array blocks, a column access circuit, and separate error correction code (ECC) engines for normal and meta data, allowing for individual generation of meta parity data, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single ECC engine is used to generate parity data for both normal data and meta data, then the device complexity is reduced, but the latency increases due to sequential processing
Solution Approach 1:
The patent divides the single ECC engine into two separate ECC engines: a first ECC engine for generating parity data for normal data, and a second ECC engine for generating parity data for meta data. This segmentation enables parallel processing of normal data and meta data, thereby reducing the overall latency without requiring a complex multi-engine architecture.
Solution Approach 2:
The patent implements preliminary action by having the first ECC engine generate parity data for normal data while the second ECC engine simultaneously generates parity data for meta data. This parallel preliminary processing eliminates the sequential dependency that would otherwise increase latency, allowing both parity generation operations to complete before data storage or retrieval operations proceed.
2Reliability
If meta data is stored without separate parity generation, then the device complexity is reduced, but the reliability decreases due to lack of error correction for meta data
Solution Approach 1:
The patent segments the error correction functionality into two distinct ECC engines, with the second ECC engine specifically dedicated to generating and managing parity data for meta data. This segmentation ensures that meta data receives the same level of error protection as normal data, thereby improving reliability without requiring a complete redesign of the storage architecture.
Solution Approach 2:
The patent applies the same error correction methodology used for normal data to meta data by implementing a second ECC engine that mirrors the functionality of the first ECC engine. This copying of the error correction mechanism to meta data ensures consistent reliability across all stored information while maintaining device complexity at an acceptable level.
3Productivity
If the memory cell array is divided into sub-array blocks for separate storage of normal data and meta data, then the productivity is improved through parallel access, but the device complexity increases
Solution Approach 1:
The patent divides the memory cell array into multiple sub-array blocks, with each block containing first memory cells for normal data and second memory cells for meta data. This segmentation enables independent and parallel access to normal data and meta data, thereby improving productivity by allowing simultaneous read/write operations without interfering with each other.
Solution Approach 2:
The patent organizes the memory cell array in a two-dimensional sub-array block structure, where the first and second memory cells are arranged in distinct regions within each block. This spatial dimensionality change allows for efficient addressing and access patterns that enable parallel operations, improving productivity while keeping the physical layout manageable.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.