Sub-block disabling circuit for 3D memory defect management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As three-dimensional memory devices grow in size, tagging defective blocks results in increasingly large amounts of memory becoming unusable, as existing methods do not efficiently manage sub-block defects within these devices.
Innovation Solution
The implementation of a sub-block disabling circuit and block disabling circuit that uses content-addressable memory to selectively disable defective sub-blocks or entire blocks, allowing for more efficient use of memory space by avoiding the need to tag each sub-block individually, especially when more than half of the sub-blocks in a block are defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If entire blocks are tagged as defective during manufacturing testing or user operations, then defective blocks are identified and isolated, but increasingly large amounts of memory become unusable as 3D memory block size increases
Solution Approach 1:
The patent divides a memory block into multiple sub-blocks and implements sub-block disabling circuits that can selectively disable only the defective sub-blocks rather than entire blocks. This segmentation allows the system to isolate defects at a finer granularity, maintaining more usable memory capacity while still ensuring reliability by preventing access to defective regions.
2Quantity of substance
If sub-block disabling circuits are implemented to selectively disable defective sub-blocks, then more memory space remains usable, but the device complexity increases due to additional disabling circuits and control logic
Solution Approach 1:
The patent combines multiple sub-block disabling circuits into a unified structure that shares common control logic and tagging mechanisms. By merging the disabling functionality across multiple sub-blocks, the system reduces the overall complexity compared to implementing independent disabling circuits for each sub-block, while still maintaining the ability to selectively disable individual defective sub-blocks.
3Quantity of substance
If more sub-blocks are disabled selectively within a block, then the amount of unusable memory is reduced, but the difficulty of detecting and measuring defective sub-blocks increases
Solution Approach 1:
The patent introduces intermediary tagging circuits and control logic that facilitate the detection and identification of defective sub-blocks. These intermediary components act as mediators between the physical sub-blocks and the control system, providing a systematic way to track, identify, and manage defective regions without requiring complex direct detection of each individual sub-block defect.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.