Sub-circuit Pattern Recognition Using Integer Arrays
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Solution Overview
Problem
The computational complexity of sub-circuit extraction in large circuit schematics increases significantly as the size of the pattern circuit or the target circuit grows, making it challenging to efficiently identify instances of a pattern circuit within a larger circuit schematic.
Innovation Solution
A method and system for sub-circuit pattern recognition in integrated circuit design, which involves encoding the pattern and target circuits, generating a cross-linked data structure using device and net integer arrays, and identifying instances through pseudo-matching and associative mapping, optimizing the search process by prioritizing devices over nets and using a dynamic hash-based decision tree scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sub-circuit extraction is performed by checking presence of pattern circuit in large circuit schematic, then pattern recognition capability is achieved, but computational complexity grows significantly as circuit size increases
Solution Approach 1:
The patent segments the sub-circuit extraction problem into multiple phases: (1) encoding phase where devices and nets are assigned integer indices, (2) data structure construction phase where cross-linked arrays are built, and (3) matching phase where pattern instances are identified. This segmentation allows each phase to be optimized independently, reducing overall computational complexity while maintaining pattern recognition capability.
Solution Approach 2:
The patent introduces intermediate data structures (device integer array, net integer array, and cross-linked arrays) as mediators between the raw circuit netlist and the pattern matching process. These intermediate structures pre-organize connectivity information, enabling efficient O(1) lookups during pattern matching and avoiding repeated complex graph traversals.
2Ease of manufacture
If straightforward comparison of devices and components is used, then implementation simplicity is maintained, but connectivity topological matching requirements increase computational burden
Solution Approach 1:
The patent performs preliminary encoding of devices and nets into integer indices, and pre-construction of cross-linked data structures that capture connectivity topology, before the actual pattern matching begins. This preliminary action transforms the complex topological matching problem into simpler array index comparisons, significantly reducing computational burden while maintaining implementation clarity.
3Adaptability or versatility
If pattern matching is performed in large circuit schematics, then design reuse capability is improved, but processing time increases with circuit size
Solution Approach 1:
The patent changes the parameter representation from symbolic device names and net names to compact integer indices. This parameter transformation enables efficient array-based operations and reduces memory access time, allowing pattern matching to scale to large circuit schematics without proportional increases in processing time.
Data Source
AI summary
A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.