Sub-cycle Phase Indicators for High Precision Event Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High precision timekeeping in network devices requires a high frequency clock, which incurs substantial power costs due to the relationship between clock power and frequency, making it challenging to distribute a 1 GHz clock across a network device for precise time stamping.
Innovation Solution
Implementing sub-cycle frequency resolution modules that generate sub-cycle phase indicators at a frequency greater than the main clock frequency, allowing for higher precision time determination using a combination of the main clock signal and sub-cycle phase indicators, while maintaining synchronization and reducing the power requirement by operating at a lower main clock frequency, such as 100 MHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high frequency clock signal (e.g., 1 GHz) is distributed across the network device, then time stamping precision is improved, but power consumption increases
Solution Approach 1:
The clock signal distribution is segmented into a main clock signal distributed at lower frequency (e.g., 100 MHz) and sub-cycle phase indicators generated locally at each processing module. This segmentation allows the main clock to provide coarse timing while local circuits provide fine-grained sub-cycle resolution, achieving high precision without distributing high-frequency clocks across the entire device.
Solution Approach 2:
Sub-cycle phase indicators act as an intermediary between the main clock signal and the event timing measurement. These indicators capture the phase information within each main clock cycle, enabling precise time stamping by combining the main clock timestamp with the sub-cycle phase data, thereby achieving high precision without requiring high-frequency clock distribution.
2Use of energy by moving object
If a lower frequency main clock signal is used, then power consumption is reduced, but time stamping precision deteriorates
Solution Approach 1:
The timing measurement is extended from a single-dimensional approach (relying solely on main clock frequency) to a two-dimensional approach by incorporating sub-cycle phase indicators. This additional dimension of phase information within each clock cycle compensates for the lower main clock frequency, enabling high precision time stamping even with a lower frequency main clock signal.
Solution Approach 2:
The system changes the parameter of clock frequency from high (1 GHz) to low (100 MHz) for the main clock signal, while simultaneously introducing a new parameter (sub-cycle phase indicators) that captures timing information within each cycle. This parameter transformation allows the system to achieve the required precision through a different combination of parameters rather than relying solely on high frequency.
Data Source
AI summary
Systems and methods are provided for determining a clock time associated with an event at a higher precision than is attainable by a main clock signal. A system includes a plurality of processing modules distributed across an integrated circuit, a main clock signal being transmitted to ones of the plurality of processing modules at a main clock frequency. A plurality of sub-cycle frequency resolution modules are disposed in corresponding ones of the processing modules, the sub-cycle frequency modules generating sub-cycle phase indicators at a frequency that is greater than the main clock frequency, the sub-cycle frequency resolution modules being configured to receive the main clock signal and to determine a clock time of an event based on a combination of the main clock and the sub-cycle phase indicators.