Delay Locked Loop with Sub-Delay Lines for Phase Clock Alignment
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Solution Overview
Problem
The initial delay value in existing delay locked loops limits the operating frequency of semiconductor devices, causing misalignment of phase clocks and restricting high-speed operations.
Innovation Solution
A delay locked loop design that includes a main delay circuit and sub-delay lines to adjust phase differences among phase clocks, allowing for a desired initial delay, enabling phase clocks to be aligned within one cycle of the internal clock and supporting high-frequency operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a delay locked loop uses a fixed initial delay value, then the circuit structure is simple, but the operating frequency is limited
Solution Approach 1:
The delay locked loop is segmented into a main delay circuit and multiple sub-delay lines. The main delay circuit generates initial phase clocks, while each sub-delay line independently adjusts the phase of specific clocks. This segmentation allows flexible phase adjustment without increasing overall circuit complexity significantly.
Solution Approach 2:
The delay locked loop transitions from a fixed initial delay value to a dynamic phase adjustment mechanism. The sub-delay lines can dynamically adjust delay values based on feedback, enabling the system to adapt to different operating frequencies and maintain optimal performance across a wide frequency range.
2Adaptability or versatility
If the initial delay value corresponds to a phase difference larger than 90°, then the delay locked loop can handle large phase shifts, but the phase clocks will not be aligned within one cycle
Solution Approach 1:
The sub-delay lines apply partial delay adjustments to specific phase clocks rather than applying a large uniform delay to all clocks. By selectively adjusting only the necessary phases with smaller delay amounts, the system achieves precise alignment within one cycle while maintaining the ability to handle large overall phase differences.
Solution Approach 2:
Different sub-delay lines apply different delay values to different phase clocks based on their specific phase error conditions. This localized adjustment approach allows each phase clock to be optimized independently, achieving precise alignment while handling varying phase differences across the system.
3Stability of the object's composition
If the delay locked loop generates four phase clocks with 90° phase difference, then the phase distribution is optimal, but the initial delay limitation prevents operation at higher frequencies
Solution Approach 1:
The system maintains the optimal 90° phase distribution dynamically through adjustable sub-delay lines. Rather than being constrained by a fixed initial delay, the sub-delay lines can dynamically adjust to maintain proper phase relationships even at higher operating frequencies where the required delay values change.
Data Source
AI summary
Embodiments disclose a delay locked loop. The delay locked loop including a main delay circuit configured to generate initial clocks by delaying an internal clock, and sub-delay lines configured to generate phase clocks having a phase difference corresponding to a desired initial delay by respectively delaying the internal clock and the initial clocks. The phase difference among the phase clocks may be adjusted according to delay values of the sub-delay lines.