Sub-device FET Architecture for Analog Circuit Matching
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Solution Overview
Problem
Conventional techniques for managing device mismatch in semiconductor devices, particularly in analog circuit design, are ineffective due to process limitations and scaling issues, leading to performance deterioration and impaired circuit function as semiconductor technologies advance.
Innovation Solution
A sub-device field-effect transistor (FET) architecture is implemented, where multiple FET sub-devices are stacked and operate in heterogeneous modes, with source-side FET sub-devices operating in the linear region to reduce threshold voltage and current sensitivity, thereby improving matching between integrated FET devices by shielding more sensitive drain-side sub-devices from random variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional matching techniques are used to design semiconductor devices with similar dimensions, then device matching is achieved, but manufacturing precision deteriorates due to process limitations and scaling issues
Solution Approach 1:
The patent divides a single FET device into multiple sub-devices (first set and second set) with different configurations. The first set includes FETs with first dimensions optimized for linear region operation, while the second set includes FETs with second dimensions optimized for saturation region operation. This segmentation allows each subset to be optimized for its specific operating region, improving overall device matching and reliability despite manufacturing process variations.
Solution Approach 2:
The patent applies different design characteristics to different subsets of FET devices. The first set of FET sub-devices is designed with specific dimensional characteristics suitable for linear region operation, while the second set is designed with different dimensional characteristics suitable for saturation region operation. This local differentiation allows each subset to perform optimally in its designated operating region, compensating for manufacturing variations.
2Power
If FET sub-devices operate in saturation mode, then high gain is achieved, but threshold voltage sensitivity increases making matching difficult
Solution Approach 1:
The patent segments the FET population into two groups: those operating in saturation mode (second set) and those operating in linear mode (first set). By separating the device population based on operating region, the patent allows saturation-mode devices to provide high gain while linear-mode devices provide stability and reduced sensitivity to threshold voltage variations, thereby improving overall matching.
Solution Approach 2:
The patent changes the operating parameter (operating region) of different FET subsets. The first set of FET sub-devices operates in the linear region where threshold voltage sensitivity is reduced, while the second set operates in the saturation region where high gain is achieved. This parameter differentiation allows the system to simultaneously achieve both high gain and improved matching.
3Manufacturing precision
If device layout is optimized for performance, then matching improves, but device complexity increases due to heterogeneous configuration
Solution Approach 1:
The patent segments the FET devices into two distinct sets with different configurations and operating regions. The first set operates in linear region with specific dimensional characteristics, while the second set operates in saturation region with different dimensional characteristics. This segmentation strategy improves matching by reducing sensitivity to threshold voltage variations while maintaining manageable complexity through systematic classification.
Data Source
AI summary
The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.