Subfin Diode Recess Profiling for Nanoribbon IC Conductance
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Solution Overview
Problem
In nanoribbon-based transistor technologies, the integration of diodes is challenging due to the limited semiconductor cross-section provided by the subfin structure, which complicates effective diode formation and increases costs and complexity when using separate fabrication processes for diodes and transistors.
Innovation Solution
The formation of subfin diodes is achieved by optimizing the etch depths in the subfin region between the nanoribbon stacks and the support structure, varying the recess depths to enhance semiconductor cross-section and contact quality, while maintaining the same etch processes used for nanoribbon-based transistors, thereby improving diode conductance and current carrying capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate fabrication processes are used for diodes and transistors, then diode formation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the fabrication processes for diodes and transistors by forming both structures simultaneously using the same etch processes. The subfin diodes are created by etching into the semiconductor substrate in the same process sequence that forms the nanoribbon transistor fins, eliminating the need for separate diode fabrication steps and reducing overall manufacturing complexity
Solution Approach 2:
The patent makes the etch process universal by designing it to perform multiple functions: etching nanoribbon fins for transistors and etching subfin regions for diodes within the same process sequence. This multi-functional approach allows a single fabrication process to create both transistor and diode structures, reducing the number of process steps required
2Ease of manufacture
If standard etch processes are used for subfin diodes, then process simplicity is maintained, but diode conductance and current carrying capability are limited
Solution Approach 1:
The patent applies local quality by creating regions of different etch depths within the subfin structure. Shallow etch regions provide mechanical support and thermal management, while deeper etch regions enhance carrier injection and improve diode conductance. This localized variation in etch depth allows the same etch process to simultaneously maintain structural integrity and improve electrical performance
Solution Approach 2:
The patent changes the etch depth parameter locally within the subfin region to optimize diode performance. By varying the etch depth from shallow in support regions to deep in active diode regions, the patent enhances current carrying capability while using the same base etch process, thus improving reliability without sacrificing process simplicity
3Reliability
If subfin structure is used for nanoribbon transistors, then transistor performance is achieved, but semiconductor cross-section for diode formation is limited
Solution Approach 1:
The patent utilizes the vertical dimension by etching downward into the substrate beneath the nanoribbon stack to create subfin diode structures. This vertical extension into the substrate provides additional semiconductor cross-section area for diode formation without interfering with the horizontal nanoribbon transistor structure, effectively adding volume for current flow in the vertical direction while maintaining transistor performance
Data Source
AI summary
Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.