Subfin Gate Isolation to Reduce Parasitic Capacitance
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Solution Overview
Problem
As integrated circuits scale downward in size, parasitic effects from semiconductor subfins beneath semiconductor regions form parasitic junctions and capacitors, reducing transistor switching speed and degrading performance.
Innovation Solution
A sacrificial material layer is deposited along the bottom of a gate trench to prevent the gate structure from forming around the sides of subfins, followed by removing the semiconductor material of the subfins from the backside and filling the resulting cavities with dielectric materials, ensuring the gate structure does not extend below the top surface of dielectric subregions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure is allowed to form around the sides of subfins to maximize transistor control, then transistor switching performance is improved, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The subfin semiconductor material is selectively removed from beneath the gate structure through backside etching, extracting the harmful parasitic capacitance source while preserving the beneficial gate control over the main fin channel
Solution Approach 2:
A sacrificial material layer is deposited on the front side before gate formation to prevent the gate structure from extending down to wrap around subfin sides, preemptively blocking the formation of parasitic capacitance junctions
2Productivity
If integrated circuits are scaled downward in size to increase device density, then productivity is improved, but parasitic effects from subfins increasingly impact device operation
Solution Approach 1:
The subfin removal is performed locally only in regions beneath the gate structure where parasitic capacitance forms, while preserving subfins in other regions that may provide beneficial strain or electrical characteristics
Solution Approach 2:
The fin structure is segmented into a main fin portion that remains for transistor operation and subfin portions that are removed to eliminate parasitics, creating a hybrid structure with optimized properties
Data Source
AI summary
Techniques are provided herein to form semiconductor devices with gate structures that do not extend below a top surface of dielectric subregions. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the fin of semiconductor material includes a subfin adjacent to a dielectric fill. A sacrificial material layer is deposited before the formation of the gate structure to prevent the gate structure from forming along the sides of the subfin. This sacrificial layer may then be removed from the backside of the structure along with the semiconductor material of the subfin. The subfin area may be replaced with one or more dielectric materials formed on the backside. As a result, the device performance is improved by lowering the parasitic capacitance caused by having the gate structure on either side of the dielectric structure replacing the subfin region.