Sub-fin isolation for GAA transistors using dielectric layers
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Solution Overview
Problem
Gate-all-around (GAA) transistor devices face issues with sub-fin leakage due to uncontrolled conduction through the substrate, leading to undesirable power consumption and decreased performance, particularly as they scale down, and using silicon on insulator (SOI) substrates is costly and not suitable for high power applications.
Innovation Solution
Implementing sub-fin isolation schemes, such as using a dielectric layer between epitaxial source/drain material and the substrate, or selectively doping the substrate to create a p-n or n-p junction, which prevents epitaxial growth and reduces sub-fin leakage, and employing an epitaxial diffusion barrier layer to prevent dopant migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If silicon on insulator (SOI) substrates are used to reduce sub-fin leakage, then sub-fin leakage is minimized, but manufacturing cost increases and suitability for high power applications decreases
Solution Approach 1:
The patent introduces an intermediary dielectric layer between the substrate and the epitaxial source/drain material to prevent direct conduction. This dielectric layer acts as a mediator that blocks sub-fin leakage current while allowing the device to use standard bulk silicon substrates, thus avoiding the high cost of SOI substrates while still achieving effective isolation.
Solution Approach 2:
The patent applies selective doping to create localized p-n or n-p junctions only in the sub-fin region where isolation is needed. This localized modification of electrical properties provides effective leakage prevention without requiring global substrate changes, enabling cost-effective implementation on standard substrates while maintaining high power application suitability.
2Productivity
If device size is scaled down to increase integration density, then productivity increases, but sub-fin leakage worsens due to uncontrolled conduction through the substrate
Solution Approach 1:
The patent implements sub-fin isolation structures and selective doping profiles during the early stages of device fabrication, before final scaling is completed. This preliminary action establishes electrical isolation barriers that prevent sub-fin leakage from developing as devices are scaled down, enabling high integration density without suffering from leakage penalties.
Solution Approach 2:
The dielectric layer serves as an intermediary barrier that becomes increasingly important as device dimensions scale down. This intermediary structure maintains electrical isolation even when lateral dimensions are reduced, allowing continued scaling to increase integration density while preventing the sub-fin leakage that would otherwise worsen with smaller device sizes.
3Ease of manufacture
If epitaxial source/drain material is grown without isolation structures, then ease of manufacture is improved, but sub-fin leakage increases due to uncontrolled conduction
Solution Approach 1:
The patent introduces a dielectric intermediary layer that can be integrated into the epitaxial growth process without significantly complicating manufacturing. This dielectric layer provides the necessary isolation function while maintaining a relatively simple fabrication flow, thus resolving the contradiction between manufacturing ease and leakage prevention.
Solution Approach 2:
The patent modifies the epitaxial growth parameters to accommodate the presence of dielectric isolation structures and selective doping regions. By adjusting growth conditions, temperature, and doping profiles, the process maintains ease of manufacture while achieving the electrical isolation needed to prevent sub-fin leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These sub-fin isolation schemes effectively minimize sub-fin leakage, improving short channel properties and enabling lower power consumption and higher performance in GAA transistor devices.
Implementation Method 1
prevents epitaxial growth
Implementation Method 2
selectively doping the substrate to create a p-n or n-p junction
Implementation Method 3
employing an epitaxial diffusion barrier layer to prevent dopant migration
Data Source
AI summary
Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g., employing one or more nanowires, nanoribbons, or nanosheets), thereby improving device performance.