Sub-fin isolation for HEMT leakage reduction
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Solution Overview
Problem
Advanced semiconductor devices, particularly high electron mobility transistors (HEMTs) using non-silicon materials, face challenges with the short channel effect (SCE) due to poor electrical isolation between the source and drain, leading to increased leakage current and reduced performance.
Innovation Solution
The implementation of heteroepitaxial sub-fin isolation structures, where a crystalline sub-fin material is undercut and backfilled with an isolation material, creating a localized sub-fin isolation that enhances electrical isolation and reduces leakage current, integrated into the fabrication process of non-silicon transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation methods are used in non-silicon transistors, then manufacturing is simpler, but leakage current increases and short channel effect worsens
Solution Approach 1:
The isolation structure is segmented into two distinct parts: a first isolation material in the source region and a second isolation material in the drain region. This segmentation allows each region to be optimized independently for reducing leakage current while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
Different isolation materials are applied to different locations (source vs. drain regions) based on their specific electrical characteristics and leakage requirements. The source region may use a material with higher dielectric constant while the drain region uses a different material, optimizing local electrical isolation without requiring complete redesign of the entire device structure.
2Reliability
If heteroepitaxial sub-fin isolation is implemented, then leakage current is reduced, but fabrication process complexity increases
Solution Approach 1:
The heteroepitaxial sub-fin isolation structures are formed preliminary to the main transistor fabrication steps. By preparing the isolation structures in advance using heteroepitaxial growth, the subsequent transistor fabrication can proceed without interruption, and the isolation structures are already in place to guide subsequent processing steps.
Solution Approach 2:
The heteroepitaxial sub-fin isolation structures serve as intermediary elements between the source/drain regions and the channel. These intermediate structures provide a controlled interface that reduces direct leakage paths while maintaining compatibility with the existing fabrication process flow through standard heteroepitaxial growth techniques.
3Reliability
If sub-fin material is undercut and backfilled, then electrical isolation is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The undercut depth and backfill material properties are carefully controlled as key parameters. By optimizing the undercut depth to be sufficient for isolation but not excessive, and by selecting backfill materials with appropriate dielectric constants and deposition characteristics, the manufacturing precision requirements are managed while achieving effective electrical isolation.
Solution Approach 2:
The isolation problem is solved by moving from a planar isolation approach to a three-dimensional sub-fin isolation approach. The undercut and backfill process creates vertical isolation structures that extend beneath the surface, providing isolation in the vertical dimension while reducing the lateral precision requirements compared to surface-level isolation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current and improves the short channel effect in non-silicon transistors, enhancing their performance and manufacturability compared to traditional isolation methods, while allowing for monolithic integration with silicon-based devices.
Implementation Method 1
forming a non-silicon crystalline device region (e.g., a transistor channel region) over an intermediate supporting structure comprising a material distinct from that of the channel device region and the substrate
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.