Subgraph Isomorphism for Computing Resource Allocation
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Solution Overview
Problem
In distributed hardware accelerator systems, data transmission between computing devices often follows inefficient paths, leading to increased processing time and cost due to suboptimal routing of code execution.
Innovation Solution
A computing system that generates a directed weighted graph of functions and processing devices, determines shortest paths between compatible functions, and constructs a subgraph isomorphism to optimize data pipeline execution, ensuring efficient routing and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted between computing devices through existing network paths, then data transmission can be performed, but the transmission path is inefficient leading to increased processing time and cost
Solution Approach 1:
The system performs preliminary actions by pre-computing shortest paths between all function pairs and pre-establishing the optimized computing resource graph before actual data transmission occurs. This allows the system to avoid inefficient paths during execution by having already determined the optimal routing structure in advance.
Solution Approach 2:
The system dynamically adapts the computing resource graph by determining shortest paths based on current network conditions and function dependencies. The graph structure is not fixed but is computed on-demand to reflect the actual optimal routing paths, allowing the system to respond to changing conditions and optimize transmission in real-time.
2Productivity
If code execution is routed through existing paths, then execution can proceed, but the routing is suboptimal increasing processing cost
Solution Approach 1:
The system changes the fundamental parameters of resource allocation by transforming the traditional fixed resource mapping into a dynamic shortest-path-based allocation. By recomputing the computing resource graph and determining optimal paths based on current conditions, the system optimizes both time and cost parameters simultaneously.
Solution Approach 2:
The system creates a virtual copy of the computing resource graph that represents the optimized routing structure. This virtual graph is used for scheduling and resource allocation decisions, allowing the system to experiment with different routing configurations without affecting the physical infrastructure, thereby optimizing cost while maintaining operational stability.
3Productivity
If the system determines shortest paths for all function pairs, then optimal routing is achieved, but the computational complexity increases
Solution Approach 1:
The system segments the complex task of finding all shortest paths into manageable steps: first constructing the computing resource graph from individual function and device information, then systematically determining shortest paths for each function pair. This segmentation allows the complex optimization to be broken down into discrete, manageable computations that can be performed efficiently.
Solution Approach 2:
The computing resource graph itself serves as an intermediary structure that simplifies the complexity management. By representing the system as a graph with functions, devices, and connections, the system transforms the complex routing problem into graph theory operations (shortest path algorithms) that have well-established efficient solutions, thereby managing complexity through structured representation.
Data Source
AI summary
A computing system is provided, including a processor configured to generate a directed weighted graph indicating a plurality of functions configured to be executed on a plurality of communicatively connected processing devices. For each of a plurality of pairs of the functions, the processor may determine a shortest path between the pair of functions. The processor may generate a second graph indicating the plurality of pairs of functions connected by the shortest paths. The processor may receive a pipeline directed acyclic graph (DAG) specifying a data pipeline of a plurality of processing stages. The processor may determine a subgraph isomorphism between the pipeline DAG and the second graph. The processor may convey, to one or more processing devices of the plurality of processing devices, instructions to execute the plurality of processing stages as specified by the subgraph isomorphism.


