Subharmonic Mixer Clock Selection With Harmonic Suppression
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Solution Overview
Problem
High frequency applications face challenges in generating and distributing clock signals close to the frequency of high frequency RF, leading to high power consumption, increased circuit area, and difficulty in processing frequencies beyond the maximum frequency capability (fMAX) of transistors, particularly in THz range applications.
Innovation Solution
A parallel switch architecture using subharmonic mixers with equally spaced LO phases is employed to generate low frequency clocks, reducing power consumption and circuit area, while suppressing unwanted harmonics through structural cancellation, allowing frequencies above fMAX to be processed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high frequency clock signals are distributed for high frequency RF applications, then frequency translation capability is improved, but power consumption increases
Solution Approach 1:
The patent divides the high frequency clock signal distribution into multiple parallel paths, each handling a specific frequency band or function. This segmentation allows selective activation of only necessary paths, reducing overall power consumption while maintaining frequency translation capability across multiple bands.
Solution Approach 2:
The patent employs variable frequency clocks and adjustable frequency multipliers that can dynamically change operating parameters. By adjusting clock frequencies to match only the currently needed RF bands, the system avoids continuous high-power consumption and enables adaptive frequency translation.
2Adaptability or versatility
If high frequency clock signals are distributed for high frequency RF applications, then frequency translation capability is improved, but circuit area increases
Solution Approach 1:
The patent designs clock distribution networks and frequency multipliers that serve multiple functions and frequency bands simultaneously. A single circuit architecture handles both low frequency and high frequency operations, as well as multiple RF bands, eliminating the need for separate dedicated circuits for each function and reducing overall circuit area.
Solution Approach 2:
The patent implements dynamically reconfigurable clock distribution networks that can adapt their topology and parameters based on which RF band is currently active. This dynamic reconfiguration allows the same physical infrastructure to serve different frequency translation needs without requiring redundant static circuitry for each possible band.
3Adaptability or versatility
If high frequency clock signals are generated for RF applications exceeding transistor fMAX, then ultra high frequency processing is enabled, but circuit implementation becomes difficult
Solution Approach 1:
The patent introduces intermediate frequency stages and sub-harmonic mixing as intermediary steps between baseband and ultra high frequency RF. Instead of directly generating frequencies above fMAX, the system uses lower frequency clocks that are easily generated, then employs frequency multiplication and mixing with intermediate signals to reach the target ultra high frequencies, making the circuit implementation feasible.
Solution Approach 2:
The patent performs preliminary frequency preparation and signal conditioning at lower frequencies where circuit implementation is easier. Clock signals are first generated at manageable frequencies, then pre-processed and prepared before being upconverted to ultra high frequencies, avoiding the need to directly generate and manipulate signals above fMAX which would be extremely difficult to implement.
Data Source
AI summary
A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.