Sub-Harmonic Ring Oscillator Phase Interpolation for Low IQ Skew
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Solution Overview
Problem
Existing clock generation techniques, such as fundamental harmonic injection locked phase interpolation, suffer from a narrow frequency locking range and poor systematic IQ skew, which limits their effectiveness in generating precise I and Q reference signals for demodulation and decoding of modulated signals.
Innovation Solution
A system and method utilizing a Ring Oscillator (RO) circuitry with differential delay stages interconnected in cascade, coupled with signal injection circuitry that applies first and second input phases based on a predetermined interpolation mapping scheme to lock the frequency of the output oscillator signal at half the frequency of the periodic input signal, achieving sub-harmonic injection locked phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fundamental harmonic injection locked phase interpolation technique is used, then the number of required input phases is reduced, but the frequency locking range becomes narrow
Solution Approach 1:
The injection locked loop is segmented into multiple differential delay stages (first, second, third, fourth stages) with selective signal injection points. By dividing the oscillator into discrete stages and injecting signals at specific points, the system achieves broader frequency locking range while maintaining reduced input phase requirements.
Solution Approach 2:
The patent transitions from fundamental harmonic injection to sub-harmonic injection, changing the dimension of the locking mechanism. By injecting at sub-harmonic frequencies and using differential delay stages with specific phase relationships, the system expands the frequency locking range beyond the limitations of fundamental harmonic approaches.
2Device complexity
If fundamental harmonic injection locked phase interpolation technique is used, then device complexity is reduced, but systematic IQ skew deteriorates
Solution Approach 1:
The patent employs asymmetric differential delay stage design where each stage introduces a controlled phase shift (e.g., 45 degrees) that is not symmetric around zero. This asymmetric phase progression, combined with selective signal injection at specific stages, enables precise IQ signal generation with minimized systematic skew while keeping the device structure relatively simple.
Solution Approach 2:
The differential delay stages are pre-configured with specific phase shift values and connection topologies before operation. By preliminarily establishing the correct phase relationships and delay characteristics in the hardware design, the system achieves accurate IQ skew control without requiring complex real-time adjustments, thus maintaining low device complexity.
3Adaptability or versatility
If sub-harmonic injection locked phase interpolation is implemented, then frequency locking range is enhanced, but device complexity increases
Solution Approach 1:
The differential delay stage structure serves multiple functions simultaneously: it provides frequency division, phase shifting, signal injection points, and IQ signal generation. By making each stage multi-functional, the system achieves broad frequency locking range without proportionally increasing device complexity, as the same structural elements perform multiple roles in the sub-harmonic injection locked loop.
Data Source
AI summary
A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.