Sub-layer Proximity Effect Modeling for Semiconductor Critical Dimension Accuracy
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Solution Overview
Problem
Conventional modeling algorithms for semiconductor device fabrication do not account for the impact of sub-layers, such as active layers positioned below gate polysilicon layers, leading to inaccuracies in critical dimension reproduction during photolithography due to optical and process proximity effects.
Innovation Solution
A method that performs first and second proximity effect modeling based on photolithography effects caused by gate and field polysilicon layers and active layers respectively, calculates pattern density using kernels like Top Hat or Gaussian, and combines results for proximity correction to manipulate mask layouts, incorporating sub-layer effects into the modeling algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional modeling algorithms are used that only consider gate and field polysilicon layers, then the modeling process is simple, but the critical dimension reproduction accuracy deteriorates due to unaccounted sub-layer proximity effects
Solution Approach 1:
The proximity effect modeling is segmented into multiple independent components: first proximity effect modeling for gate and field polysilicon layers, and second proximity effect modeling for sub-layers. Each component is modeled separately using dedicated algorithms and parameters, then combined to achieve comprehensive accuracy without overwhelming complexity in a single monolithic model.
Solution Approach 2:
A sub-layer proximity effect modeling component is introduced as an intermediary between the conventional polysilicon layer modeling and the final critical dimension prediction. This intermediary layer specifically captures the optical and process proximity effects from active layers and other sub-layers, filling the gap in conventional models and improving overall accuracy.
2Manufacturing precision
If multi-layer proximity effect modeling is performed to account for sub-layers, then the accuracy of critical dimension reproduction improves, but the computational complexity and processing time increase
Solution Approach 1:
The computational workload is segmented into separate modeling passes for different layers. The first proximity effect modeling handles gate and field polysilicon, while the second handles sub-layers. This segmentation allows for optimized computational approaches in each pass and enables parallel processing where applicable, reducing overall processing time compared to a single comprehensive model.
Solution Approach 2:
The modeling approach applies partial action by focusing computational resources on the most critical layers that have the greatest impact on critical dimension accuracy. Rather than modeling every possible effect from all layers with equal detail, the method prioritizes sub-layers and polysilicon layers that contribute most significantly to proximity effects, achieving high accuracy with reduced computational overhead.
Data Source
AI summary
A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.