Sublithographic FinFET via Solid Phase Epitaxy
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Solution Overview
Problem
Conventional finFETs are limited by minimum lithographic dimensions, aspect ratio, and line edge roughness, which restrict fin width and pattern density, and are further degraded by parasitic capacitance from dielectric fin caps.
Innovation Solution
A semiconductor structure is formed using a dielectric mandrel with vertical sidewalls on a single crystalline layer, where an amorphous semiconductor material is deposited and converted to an epitaxial layer via solid phase epitaxy, allowing for the creation of sublithographic width semiconductor fins with uniform thickness, reducing parasitic capacitance and improving finFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to form semiconductor fins, then the fin width is limited by minimum lithographic dimensions, but this limits the pattern density and on-current per unit device area
Solution Approach 1:
The patent transitions from planar lithographic patterning to three-dimensional self-aligned patterning using solid phase epitaxy. The amorphous semiconductor layer is deposited conformally on vertically extending mandrels, and the epitaxial conversion occurs in a direction substantially perpendicular to the mandrel sidewalls, enabling fin widths below lithographic limits while maintaining alignment precision.
Solution Approach 2:
The solid phase epitaxy process is self-aligned to the mandrel sidewalls, automatically defining the fin width and position without requiring additional lithographic steps. The epitaxial conversion front propagates uniformly from the crystalline seed layer, self-regulating the fin dimensions based on the mandrel geometry and layer thickness.
2Power
If higher aspect ratio fins are formed to increase on-current, then the on-current per unit device area improves, but the etch process selectivity and pattern collapse limitations restrict the maximum achievable aspect ratio
Solution Approach 1:
Dielectric mandrels with vertical sidewalls are formed beforehand to serve as self-aligned masks and spacing structures. These pre-formed mandrels define the fin geometry and provide mechanical support during subsequent processing, enabling higher aspect ratios without pattern collapse while maintaining etch selectivity.
3Manufacturing precision
If conventional etch processes are used to transfer patterns, then the pattern transfer is achieved, but line edge roughness is introduced during pattern transfer
Solution Approach 1:
The patent replaces the mechanical/chemical etching process with a solid phase epitaxial conversion process. Instead of removing material to define fins, the amorphous layer is converted to crystalline material in a controlled front propagation process that produces smooth fin sidewalls and eliminates line edge roughness inherent in etch-based patterning.
4Reliability
If dielectric fin cap portions are added to protect fins, then the fin structure is protected, but parasitic capacitance increases and fin FET performance degrades
Solution Approach 1:
The patent removes the dielectric fin cap portion from the structure by using the mandrel as a sacrificial element that is eliminated after serving its purpose. The amorphous semiconductor layer is converted to epitaxial fins that directly contact the substrate, eliminating the need for protective caps and the associated parasitic capacitance while maintaining fin integrity through the self-aligned epitaxial process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of semiconductor fins with sublithographic widths and uniform thickness, enhancing on-current density and reducing parasitic capacitance, thereby improving the performance and pattern density of finFETs.
Implementation Method 1
Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer
Data Source
AI summary
A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.