SubLVDS Receiver Circuit With Clamp Control for Low-Voltage Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Long signal paths in digital transmission systems require large power consumption and significant circuitry, leading to inefficiencies in voltage level shifting and electrostatic discharge protection, especially in compact camera port 2 (CCP2) applications where low voltage differential signaling (LVDS) standards are used.
Innovation Solution
A rail-to-rail high speed subLVDS amplifier with a clamp circuit is designed to operate at low power supply voltages, using a voltage shifter and differential pairs to maintain constant gain and minimize jitter, while employing current mode logic and transistor matching to reduce parasitic loading and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LVDS circuitry is used for long signal paths, then voltage level shifting and electrostatic discharge protection are achieved, but power consumption increases and large pad areas are required
Solution Approach 1:
The patent changes the operating voltage parameter from conventional LVDS levels to subLVDS levels (lower voltage), which reduces power consumption while maintaining signal integrity through optimized circuit design at the new voltage level
Solution Approach 2:
The receiver circuit is segmented into distinct functional blocks (differential amplifier, clamp circuit, differential to single-ended converter) that can be independently optimized, allowing each segment to operate efficiently at subLVDS voltage levels
2Reliability
If conventional LVDS circuitry is used for long signal paths, then voltage level shifting and electrostatic discharge protection are achieved, but large pad areas and large passive components are required
Solution Approach 1:
By operating at subLVDS voltage levels, the patent reduces the voltage swing requirements, which allows for smaller capacitor values and reduced pad areas while maintaining the same level of protection and signal integrity
Solution Approach 2:
The patent uses smaller, less expensive passive components that are sufficient for subLVDS operation, replacing large, costly components required by conventional LVDS designs
3Speed
If rail-to-rail preamplifier is used, then high speed performance is achieved, but jitter increases due to propagation delay variations
Solution Approach 1:
The clamp circuit provides feedback control by detecting the common mode voltage level and adjusting the amplifier operation accordingly, which stabilizes propagation delay and reduces jitter while maintaining high-speed performance
Solution Approach 2:
The clamp circuit maintains a stable common mode voltage level (equipotential condition) throughout the signal range, which equalizes propagation delays across different signal conditions and minimizes jitter
4Use of energy by stationary object
If lower power supply voltages are used, then power consumption is reduced, but maintaining constant gain and signal integrity becomes difficult
Solution Approach 1:
The amplifier uses dynamic biasing and clamping mechanisms that adapt to the lower voltage conditions, automatically adjusting operating points to maintain constant gain and signal integrity across the subLVDS voltage range
Data Source
AI summary
A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.