Sub-matrix Error Detection for Unbalanced Memory Errors
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Solution Overview
Problem
Interleaving schemes in memory systems can lead to catastrophic data loss when one error-prone memory device affects multiple codewords, as errors are not evenly distributed, causing irrecoverable data due to disproportionate impact on certain codewords.
Innovation Solution
Implementing a sub-matrix error detection mechanism using a modified parity check matrix with sub-matrices to estimate error propensities of individual memory portions, allowing for remedial operations such as adjusting reading signal values and soft information to mitigate unbalanced error conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interleaving scheme is used to normalize error distribution, then the average number of errors per codeword is reduced, but the risk of catastrophic data loss from a single error-prone memory device increases
Solution Approach 1:
The patent divides the error detection process into segments by using sub-matrices in the parity check matrix to independently evaluate error propensities of different memory portions. This segmentation allows identification of specific error-prone segments without requiring catastrophic failure of entire codewords, thus resolving the contradiction between normalized error distribution and catastrophic data loss risk.
Solution Approach 2:
The patent performs preliminary error propensity estimation using sub-matrix operations before attempting full codeword correction. By pre-identifying error-prone memory portions through sub-matrix syndrome calculations, the system can take preventive actions (such as skipping problematic portions or applying targeted correction) before catastrophic data loss occurs, thus resolving the contradiction.
2Reliability
If error control coding is used to limit uncorrectable errors, then data integrity is improved, but the complexity of the error control engine increases
Solution Approach 1:
The patent segments the parity check matrix into sub-matrices, each responsible for evaluating specific portions of codewords. This segmentation simplifies the error control engine by allowing independent sub-matrix operations rather than requiring full-matrix processing, thus reducing computational complexity while maintaining data integrity through systematic error evaluation.
Solution Approach 2:
The patent applies local quality by using different sub-matrices with potentially different properties to evaluate different memory portions. This allows the error control engine to adapt its evaluation strategy to local characteristics of memory devices, improving data integrity while avoiding the need for a universally complex error control mechanism.
Data Source
AI summary
Mechanisms are provided for detecting whether at least one of two or more portions of memory (e.g. chips, blocks, sectors, planes, pages, word lines, etc.) are more error-prone than the others, when portions of codewords are interleaved across the two or more portions of memory. Some implementations also enable various remedial operations that can be selectively employed in response to detecting an unbalanced error condition in order to reduce the risks associated with interleaving portions of codewords across two or more portions of memory.