Sub-Memory Array Layout With Overlapping Local Sense Amplifiers
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Solution Overview
Problem
Existing memory devices face challenges in efficiently arranging word line drivers and sense amplifier circuits due to irregularly sized independent cells, leading to increased device size and reduced reliability and productivity.
Innovation Solution
The memory device incorporates a cell on peripheral (COP) structure with overlapping local sense amplifier circuits and bit lines, optimizing the arrangement of sub-memory arrays and peripheral circuits to enhance area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent cell arrays of irregular sizes are used to increase memory reliability and productivity, then memory reliability and productivity are improved, but the overall size of the memory device increases due to inefficient arrangement of word line drivers and sense amplifier circuits
Solution Approach 1:
The patent combines multiple sense amplifier circuits into a shared peripheral circuit region that serves multiple sub-memory arrays. The sense amplifier circuits are arranged to handle bit lines from different sub-memory arrays simultaneously, reducing the total area required for peripheral circuits while maintaining support for irregularly sized independent cell arrays.
Solution Approach 2:
The peripheral circuit region is designed with universal sense amplifier circuits that can serve multiple functions across different sub-memory arrays. These circuits are configured to handle various bit line configurations and can adapt to different sub-memory array sizes, providing multi-functional support that reduces overall device area.
2Reliability
If independent cell arrays of irregular sizes are used to increase memory reliability and productivity, then memory reliability and productivity are improved, but the arrangement of word line drivers and sense amplifier circuits becomes inefficient
Solution Approach 1:
The patent segments the memory device into distinct memory cell regions and a shared peripheral circuit region. Word line drivers are placed within or adjacent to their respective sub-memory arrays, while sense amplifier circuits are consolidated in the peripheral region. This segmentation allows independent optimization of each segment while simplifying the overall arrangement.
Solution Approach 2:
The patent utilizes three-dimensional arrangement by placing sense amplifier circuits in a peripheral circuit region that overlaps vertically with memory cell regions. This vertical stacking approach allows sense amplifier circuits to serve multiple sub-memory arrays without increasing the planar footprint, effectively using the third dimension to reduce arrangement complexity.
Data Source
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AI summary
A memory device is provided. The memory device includes a memory cell region including a first sub-memory array (SMA11) and a second sub-memory array (SMA12) arranged in a first direction (D2), and a peripheral circuit region including a first local sense amplifier circuit that at least partially overlaps the first and second sub-memory arrays (SMA11, SMA12) in a second direction (D3). The first sub-memory array (SMA11) includes first volatile memory cells electrically connected to a first word line and to respective ones of first bit lines. The second sub-memory array (SMA12) includes second volatile memory cells electrically connected to a second word line and to respective ones of second bit lines. The first local sense amplifier circuit is electrically connected to at least one of the first bit lines and to at least one of the second bit lines. A number of the first bit lines is equal to a number of the second bit lines.