Submicron Capacitor With Silicon Oxy-Nitride Dielectric
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Solution Overview
Problem
Attaining high capacitance density, low capacitance variation over voltage ranges, high reliability, and compatibility with interconnect patterning steps in microelectronic devices with capacitors having a metal interconnect lower plate is challenging due to limitations in capacitor dielectric layer thickness and composition.
Innovation Solution
A microelectronic device with a capacitor dielectric layer comprising a lower silicon dioxide layer, a silicon oxy-nitride layer with an average index of refraction of 1.85 to 1.95, and an upper silicon dioxide layer, where the silicon oxy-nitride layer serves as an anti-reflection layer during photolithography, enabling efficient patterning and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor dielectric layer uses a single-layer structure with limited thickness, then the fabrication process is simple, but the capacitance density and reliability are insufficient
Solution Approach 1:
The capacitor dielectric layer is divided into three distinct sub-layers: a lower silicon dioxide layer (3-7 nm), a middle silicon oxy-nitride layer (20-30 nm), and an upper silicon dioxide layer (8-12 nm). This segmentation allows each layer to contribute specific properties - the lower layer provides interface quality, the middle layer provides high dielectric constant and anti-reflection properties, and the upper layer provides breakdown voltage - achieving high reliability without excessive overall thickness
Solution Approach 2:
The dielectric structure uses a composite of silicon dioxide and silicon oxy-nitride materials. The silicon oxy-nitride layer has a dielectric constant of 3.5-4.5 and serves as both a high-k dielectric material for capacitance and an anti-reflection coating material for photolithography compatibility. This composite approach enables simultaneous achievement of high capacitance density, reliability, and fabrication compatibility
2Reliability
If the capacitor dielectric layer is made thicker to increase breakdown voltage, then reliability improves, but capacitance density decreases
Solution Approach 1:
The composite dielectric structure achieves a breakdown voltage greater than 20 volts while maintaining capacitance density greater than 1 fF/μm². The silicon oxy-nitride layer with dielectric constant of 3.5-4.5 provides high capacitance in a thin profile (20-30 nm), while the silicon dioxide layers provide excellent breakdown characteristics. This composite approach decouples the trade-off between thickness and capacitance
Solution Approach 2:
Different regions of the dielectric structure are optimized for different functions: the lower silicon dioxide layer (3-7 nm) optimizes the interface with the lower plate for reliability, the middle silicon oxy-nitride layer (20-30 nm) maximizes capacitance density with its higher dielectric constant, and the upper silicon dioxide layer (8-12 nm) provides breakdown voltage protection. This local optimization allows simultaneous achievement of high capacitance density and high breakdown voltage
3Manufacturing precision
If a separate anti-reflection layer is added for photolithography, then patterning precision improves, but device complexity and fabrication cost increase
Solution Approach 1:
The middle silicon oxy-nitride layer serves multiple functions simultaneously: (1) it acts as the high-k dielectric material providing capacitance, (2) it serves as the anti-reflection coating for photolithography patterning of the lower plate, and (3) it provides stress management for the metal interconnect layer. This multi-functionality eliminates the need for a separate anti-reflection layer, reducing fabrication complexity and cost while maintaining patterning precision
Solution Approach 2:
The anti-reflection function is merged into the capacitor dielectric structure by using the silicon oxy-nitride layer as both the dielectric and the anti-reflection coating. This merging of functions allows the photolithography process to pattern the lower plate with high precision (achieving submicron pitch) without requiring an additional anti-reflection layer, thus simplifying the overall fabrication process
4Quantity of substance
If the lower plate is made larger to increase capacitance, then capacitance density improves, but area occupied increases
Solution Approach 1:
The use of silicon oxy-nitride with dielectric constant of 3.5-4.5 in the middle layer significantly increases the capacitance density without increasing the physical area of the capacitor. The high-k material provides greater capacitance per unit area, allowing capacitance density greater than 1 fF/μm² to be achieved while occupying minimal area on the chip
Solution Approach 2:
The capacitor structure optimizes the dielectric properties locally between the plates by using the high-k silicon oxy-nitride layer in the critical region where the electric field exists. This local enhancement of dielectric constant maximizes capacitance density within the confined space between the upper and lower plates, achieving high capacitance without increasing the lateral dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a capacitance density greater than 1 fF/μm², breakdown voltage greater than 20 volts, and reliable operation for over 10 years with minimal capacitance variation across a 10-volt range, while simplifying the photolithographic process and reducing nitrogen poisoning risks.
Implementation Method 1
The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nm. The lower silicon dioxide layer, the silicon oxy-nitride layer, and a portion of the upper silicon dioxide layer extend past the upper plate on the lower plate and serve as an anti-reflection layer
Data Source
AI summary
An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.