Submicron Gate Structure for High-PPI Display Panels
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Solution Overview
Problem
The challenge in display panel manufacturing is to minimize the size and occupied area of the array substrate, particularly for ultra-high pixels per inch (PPI) and submicron-level devices, such as those used in virtual reality (VR) and augmented reality (AR) displays, while maintaining high aperture ratio and resolution.
Innovation Solution
The display panel design includes an active layer with a channel layer, a gate of equal width to the channel layer, and a gate auxiliary structure, where the gate width is less than 1 micrometer, and the gate auxiliary structure is disposed adjacent to the gate, assisting in the formation of the gate and reducing the channel layer length, thereby minimizing the overall panel size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate width is reduced to less than 1 micrometer, then the channel layer length is reduced and panel area is minimized, but the manufacturing precision requirements increase significantly
Solution Approach 1:
The patent introduces a gate auxiliary structure that extends in the second direction (vertical dimension) adjacent to the gate along the first direction (horizontal dimension). This dimensional extension allows the gate auxiliary structure to provide structural support and define the gate region without requiring increased horizontal width, thus maintaining reduced panel area while enabling precise submicron gate dimensions through vertical structural reinforcement.
Solution Approach 2:
The gate auxiliary structure serves as an intermediary element between the gate and the channel layer. It mediates the structural relationship by providing a framework that holds the gate in precise position with width less than 1 micrometer, while also defining the channel layer region. This intermediary structure makes it feasible to achieve and maintain such precise submicron dimensions during manufacturing.
2Speed
If the channel layer length is reduced, then the migration rate is improved and panel size is minimized, but the device complexity increases for ultra-high PPI
Solution Approach 1:
The patent segments the gate structure into two distinct parts: the gate itself and the gate auxiliary structure. This segmentation allows the gate to be minimized in width for fast migration rate, while the auxiliary structure provides the necessary structural complexity for precise positioning and manufacturing control in ultra-high PPI applications. The channel layer is also segmented with transition layers at its ends, allowing independent optimization of each region.
Solution Approach 2:
The patent applies different structural qualities to different regions: the gate region has minimal width for speed optimization, the gate auxiliary structure has extended vertical dimension for positioning precision, and the channel layer has transition layers at ends for electrical control. This local differentiation allows the system to achieve high migration rate in the channel while managing overall device complexity through region-specific design.
3Area of moving object
If the gate width is minimized to increase aperture ratio, then the panel resolution is enhanced, but the manufacturing difficulty increases for submicron levels
Solution Approach 1:
The gate auxiliary structure extends in the second direction (vertical dimension) to provide structural support for the submicron gate, enabling precise manufacturing through vertical process control rather than relying solely on horizontal lithography precision. This dimensional shift makes submicron gate fabrication more manageable.
Solution Approach 2:
The gate auxiliary structure acts as a manufacturing intermediary that simplifies the fabrication of submicron gates. It provides a larger vertical footprint that can be more easily patterned and aligned, serving as a template or reference structure that enables subsequent precise formation of the narrow gate with width less than 1 micrometer.
Data Source
AI summary
A display panel and a display device are provided. The display panel includes: an active layer, a gate, and a gate auxiliary structure. The active layer is disposed along a first direction and includes a channel layer. The gate is disposed above the channel layer and a width of the gate along the first direction is equal to a length of the channel layer along the first direction. The gate auxiliary structure is disposed adjacent to the gate. The width of the gate along the first direction is less than 1 micrometer.