Submission Queue Buffers With Dynamic Prefetch for Memory Sub-Systems

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Solution Overview

Problem

Conventional memory sub-systems face challenges in maximizing bandwidth utilization and minimizing latency in highly threaded environments with variable queue depths, particularly in computing systems performing artificial neural network (ANN) and artificial intelligence (AI) tasks, due to unpredictable thread patterns and varying read sizes.

Innovation Solution

Implementing a dynamic prefetch mechanism in memory sub-systems with fast random access memory, using dedicated queue pairs and speculative prefetching to predict and buffer data chunks based on sequential access patterns, dynamically adjusting buffer sizes and allocation to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional memory sub-systems use fixed buffer allocation, then device complexity is reduced, but bandwidth utilization is limited and latency increases in highly threaded environments

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer allocation where the memory sub-system adjusts buffer sizes and allocation strategies based on real-time queue depth measurements and access patterns. Buffers are dynamically resized and reassigned to submission queues according to current workload conditions, enabling optimal bandwidth utilization without fixed constraints

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent divides the buffer pool into multiple submission queue-specific buffers, with each buffer independently managed and sized according to its queue's characteristics. This segmentation allows parallel optimization of each queue's buffer allocation, improving overall bandwidth utilization while maintaining manageable complexity through modular structure

Inventive Principle:
Principle #1Segmentation

2Loss of time

If memory sub-systems use speculative prefetching, then latency is reduced, but buffer management complexity increases

Engineering Contradiction:
Improveaccess latencyVSAvoidprefetch management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements speculative prefetching where the memory sub-system proactively loads data into buffers before actual requests are made. By analyzing access patterns and predicting future needs, the system performs preliminary data retrieval and buffering operations, significantly reducing access latency for sequential and predictable access patterns

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs feedback mechanisms where the memory sub-system continuously monitors queue depth, access patterns, and buffer utilization statistics. This feedback information is used to dynamically adjust prefetching strategies and buffer allocation, optimizing latency reduction while preventing excessive complexity through data-driven control

Inventive Principle:
Principle #23Feedback

3Productivity

If buffer sizes are dynamically adjusted, then bandwidth utilization improves, but device complexity increases

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidbuffer size management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service buffer management where the memory sub-system automatically adjusts buffer sizes based on monitored statistics without external intervention. The system uses its own performance data (queue depth, access patterns, throughput) to autonomously optimize buffer allocation, improving bandwidth utilization while minimizing management complexity through automated control

Inventive Principle:
Principle #25Self-service

4Reliability

If dedicated buffers are allocated to each submission queue, then performance consistency improves, but device complexity increases

Engineering Contradiction:
Improveperformance consistencyVSAvoidbuffer allocation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the buffer resources into dedicated pools for each submission queue, with each queue receiving its own allocated buffer space. This segmentation ensures performance consistency by guaranteeing dedicated resources to each queue while maintaining manageable complexity through systematic allocation strategies and statistical monitoring

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260056662A1Buffers Configured for Individual Submission Queues in Communications between a Memory Sub-System and a Host System
Publication Date: 2026.02.26 MICRON TECHNOLOGY INC
  • US20260056662A1 patent drawing
  • US20260056662A1 patent drawing
  • US20260056662A1 patent drawing

AI summary

A memory sub-system having: a random access memory; a storage medium accessible to a host system using commands communicated via a plurality of submission queues to the memory sub-system; and a circuit configured to allocate, from the random access memory, one or more buffers that are associated respectively with one or more submission queues among the plurality of submission queues. The memory sub-system can: load data from the storage medium of the memory sub-system to a first buffer among the one or more buffers; retrieve, from a first submission queue associated with the first buffer among the plurality of the submission queues, a first command configured to access the storage medium; and execute the first command using the data in the first buffer.