Submodule Semiconductor Package Vias for Sintering Deformation Resistance
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Solution Overview
Problem
Existing semiconductor packages face challenges in resisting deformation during pressure-assisted sintering processes, which can lead to damage and inefficiencies in the manufacturing of semiconductor devices.
Innovation Solution
The semiconductor device design includes a die coupled over a lead frame, a redistribution layer (RDL) over the die, a first plurality of vias between the RDL and the die, and a second plurality of vias directly over the lead frame, which are electrically isolated from the die. This configuration enhances structural support and prevents deformation during sintering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional semiconductor package structure is used, then the manufacturing process is simple, but the package deforms during pressure-assisted sintering
Solution Approach 1:
The package structure is segmented into functionally distinct components: a first plurality of vias for electrical connection between the RDL and die, and a second plurality of vias for structural support and thermal management that are electrically isolated from the die. This segmentation allows each via group to be optimized for its specific function, with the second via group providing deformation resistance during sintering without complicating the electrical connection scheme.
Solution Approach 2:
Different regions of the package are assigned different properties: the second plurality of vias is positioned adjacent to the outer edge and electrically isolated to provide localized structural reinforcement and thermal pathways. The RDL is configured with specific thickness (at least 50 um) and via proximity (less than 100 um from via edges) to provide localized structural support where deformation is most likely to occur during pressure-assisted sintering.
2Strength
If the RDL is made thicker to prevent deformation, then structural support is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The RDL thickness is specified as at least 50 um, which is a parameter change from conventional thinner RDL designs. This increased thickness provides sufficient structural support to resist deformation during pressure-assisted sintering while maintaining manufacturability. The parameter is set high enough to provide mechanical strength but not so high as to create excessive manufacturing difficulty or material waste.
3Productivity
If vias are positioned closer to the RDL edge to improve electrical connection, then connection efficiency increases, but the RDL becomes more prone to deformation
Solution Approach 1:
The via structure is segmented into two functional groups: the first plurality of vias is positioned close to the RDL edge (less than 100 um from via edges) to optimize electrical connection efficiency, while the second plurality of vias is positioned adjacent to the outer edge and electrically isolated to provide structural reinforcement. This segmentation allows the RDL to benefit from both close via proximity for electrical performance and additional peripheral via support for mechanical stability during sintering.
Data Source
AI summary
Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.