Sub-module Physical Synthesis for EDA Design Refinement
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Solution Overview
Problem
Current electronic-design-automation (EDA) techniques face inefficiencies and errors when refining sub-modules of digital circuit designs due to the need for one-to-one correspondence between functional and physical implementations, leading to complex and time-consuming processes that require rebuilding entire sub-circuits.
Innovation Solution
The introduction of sub-module physical synthesis independent of physical hierarchy, utilizing 'porosity DEF' and 'inverse ILM' concepts to allow targeted refinement of sub-modules within the context of the larger design, enabling seamless integration and reducing the need for rebuilding the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one-to-one correspondence between functional and physical sub-circuits is maintained, then design consistency is preserved, but designer efficiency deteriorates and build time increases
Solution Approach 1:
The patent segments the physical implementation into hierarchical levels (full physical implementation, partial physical implementation, and functional model) allowing selective refinement. The designer can work on a subset of sub-circuits in the functional model without requiring corresponding physical sub-circuit definitions, thus breaking the rigid one-to-one correspondence while maintaining overall design consistency through the hierarchical structure.
Solution Approach 2:
The patent enables partial action by allowing the designer to perform physical synthesis on only the necessary subset of sub-circuits (those without defined physical implementations) rather than requiring synthesis of the entire design. This partial synthesis approach maintains design consistency for the portions that need it while avoiding unnecessary work on already-defined physical sub-circuits, thereby improving efficiency.
2Manufacturing precision
If entire sub-circuit is rebuilt to refine a small portion, then refinement completeness is achieved, but time consumption and error risk increase
Solution Approach 1:
The patent extracts and isolates the specific sub-module that requires refinement from the larger sub-circuit context. By identifying sub-circuits without defined physical implementations and selecting only those for synthesis, the system extracts the minimal necessary portion for refinement. This allows the designer to refine only the required small portion while maintaining refinement completeness, avoiding the time-consuming process of rebuilding the entire sub-circuit.
3Stability of the object's composition
If physical hierarchy is strictly enforced, then implementation structure is maintained, but flexibility for targeted refinement is reduced
Solution Approach 1:
The patent introduces dynamic flexibility into the physical hierarchy by allowing the designer to selectively define or omit physical sub-circuit definitions based on refinement needs. The system adapts the hierarchical structure dynamically - maintaining strict hierarchy where physical implementations are defined, and allowing functional modeling flexibility where they are not. This dynamic approach preserves implementation structure stability while enabling adaptability for targeted refinement without requiring complete hierarchical redefinition.
Data Source
AI summary
A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.