Submount with Exposed Gold Bump Electrodes
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Solution Overview
Problem
Conventional semiconductor modules with submounts have large parasitic capacitance and pitch, making it difficult to manufacture high-density submounts due to electrode formation on both surfaces and through-hole land portions, which requires additional electrode formation on side surfaces for electrical connections.
Innovation Solution
A submount design featuring a substrate with electrodes and semiconductor elements connected by wires, where gold bumps are formed and encapsulated in resin, with exposed cut surfaces acting as electrodes, eliminating the need for side surface electrode formation and using a harder resin to protect the components during wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrodes are formed on both surfaces and through-hole land portions of the submount, then electrical connection between IC and semiconductor element is achieved, but parasitic capacitance becomes large and pitch increases
Solution Approach 1:
The invention extracts the electrode function from the traditional planar electrode structure and relocates it to the side surface through exposed bump structures. This removes the harmful effect of large parasitic capacitance associated with traditional top-and-bottom electrode configurations while maintaining electrical connectivity.
Solution Approach 2:
The invention transitions the electrode configuration from a two-dimensional planar arrangement (top and bottom surfaces) to a three-dimensional structure where exposed bumps on the side surface serve as electrodes. This dimensional change reduces the electrode area and parasitic capacitance while enabling high-density interconnections.
2Reliability
If through-hole land portions are used for electrical connection, then IC and submount can be connected, but pitch becomes large and high-density manufacturing is difficult
Solution Approach 1:
The invention moves the electrical connection interface from the planar dimension (through-hole land portions on substrate surfaces) to the vertical dimension (exposed bumps on side surface). This enables much smaller pitch and higher manufacturing density while maintaining reliable electrical connection between IC and submount.
3Reliability
If resin encapsulation is applied to protect components during wire bonding, then mechanical protection is provided, but soft resin may deform under wire bonding stress
Solution Approach 1:
The invention uses a composite resin structure with a hard resin layer specifically positioned to withstand wire bonding stress, while softer resin provides overall encapsulation and protection. This composite approach combines the strength needed for wire bonding with the protective benefits of resin encapsulation.
Solution Approach 2:
The invention applies different resin hardness properties to different regions: a hard resin layer is placed in the wire bonding region to resist deformation during the bonding process, while other regions may use softer resin for flexibility and protection. This localized property differentiation resolves the contradiction between protection and deformation resistance.
Data Source
AI summary
The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps, are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.