Subnet Defect Diagnostics via Fault Compositing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fault simulation methods are impractical for diagnosing defects in modern semiconductor chip designs due to the exponential growth of subnet faults, especially in fan-out nets with multiple receivers, and require either extensive modeling or physical circuit design mapping, which can be costly or unavailable.
Innovation Solution
A method and system for subnet defect diagnostics through fault compositing, where two or more faults are combined to estimate the behavior of a virtual fault without simulating subnet faults, allowing for efficient modeling and scoring of defects in fan-out nets by creating a composite fault that explains the highest number of failures with a low conflict count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fan-out subnet fault models are created for each subset of receivers, then defect diagnosis accuracy is improved, but the number of faults to be modeled and simulated grows exponentially
Solution Approach 1:
The patent segments the fan-out net into multiple subnets, each feeding a specific subset of receivers. Instead of creating fault models for all possible receiver combinations, it divides the problem into manageable subnet segments. This segmentation allows the system to model only the relevant subnets that actually exist in the physical design, reducing the exponential growth of fault models while maintaining diagnostic accuracy for defects in those specific subnets.
Solution Approach 2:
The patent performs preliminary analysis of the physical circuit design to identify which subsets of receivers are actually fed by common subnets before creating fault models. This preliminary action prevents the system from generating unnecessary fault models for receiver combinations that don't correspond to actual physical subnets, thereby reducing the total number of faults to be modeled while preserving diagnostic capability for real defects.
2Device complexity
If physical circuit design mapping is used to reduce the number of subnet faults, then modeling complexity is reduced, but mapping information may be lost or unavailable after manufacturing
Solution Approach 1:
The patent creates a logical copy or representation of the physical circuit design's subnet structure through fault simulation models. Instead of relying on physical design mapping information that may be lost after manufacturing, it reconstructs the essential subnet topology information through fault simulation and analysis of test results. This copying approach preserves the necessary structural information for defect diagnosis without requiring the original physical design files.
Solution Approach 2:
The patent uses fault simulation results and test data as an intermediary to bridge the gap between the physical circuit design and the defect diagnosis process. Rather than directly requiring physical design mapping information, it uses the intermediary step of fault simulation to infer subnet structure and identify defects. This intermediary approach allows defect diagnosis to proceed even when original mapping information is unavailable.
3Reliability
If all possible subnet faults are simulated, then complete defect coverage is achieved, but computational resources and time are excessively consumed
Solution Approach 1:
The patent applies partial action by simulating only the subset of faults that are relevant to actual physical subnets rather than all possible receiver combinations. It performs exactly enough fault simulation to cover the actual subnet structure identified through preliminary analysis, avoiding excessive simulation of unnecessary fault scenarios. This partial approach achieves complete coverage of actual defects while maintaining computational efficiency.
Data Source
AI summary
A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The composite fault is assigned a score based on the composite conflict count, which score determines a candidate composite that best explains the faults of the list of faults. This procedure may be repeated to explain all the failures.