Sub-Pixel Circuit Integrating Capacitor Functions to Cut Mask Steps
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Solution Overview
Problem
The separate formation processes for transistors and capacitors in display devices require additional masks and time, increasing manufacturing complexity and cost.
Innovation Solution
A sub-pixel design that integrates transistors with capacitor functionality, utilizing a semiconductor layer formed on a silicon substrate, with specific transistor configurations and gate insulating layers to combine these components into a single process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors and capacitors are formed through separate processes, then the capacitor can be formed with dedicated structures, but additional masks and time are required
Solution Approach 1:
The patent merges the transistor and capacitor formation processes into a single integrated process. The capacitor is formed by utilizing the gate electrode and gate insulating layer of the transistor structure itself, eliminating the need for separate capacitor formation steps, additional masks, and extra processing time while maintaining manufacturing precision
2Manufacturing precision
If transistors and capacitors are formed through separate processes, then each component can be optimized independently, but the manufacturing complexity increases
Solution Approach 1:
The gate electrode and gate insulating layer of the transistor serve dual functions: as the transistor's gate structure and as the capacitor's electrodes and dielectric layer. This multi-functionality reduces manufacturing process complexity by eliminating dedicated capacitor formation steps while maintaining the ability to optimize both transistor and capacitor performance through the shared structure
3Manufacturing precision
If transistors and capacitors are formed through separate processes, then the capacitor can be formed with dedicated electrodes, but additional masks are required
Solution Approach 1:
The capacitor electrodes are merged with the transistor gate electrode, eliminating the need for separate capacitor electrode formation masks. The same mask used to define the transistor gate pattern also defines the capacitor electrode pattern, reducing the total number of masks required while maintaining precise electrode alignment through the shared patterning process
Data Source
AI summary
A sub-pixel includes a sixth transistor including a gate, a source electrode, and a drain electrode, wherein the gate is connected to one of a second transistor and a second node, and wherein the source electrode and the drain electrode are connected to the other of the second transistor and the second node. The sub-pixel further includes a seventh transistor including a gate, a source electrode, and a drain electrode, wherein the gate is connected to one of the second node and a fourth power line, and wherein the source electrode and the drain electrode are connected to the other of the second node and the fourth power line.