Sub-Pixel Capacitor Layout to Mitigate Parasitic Voltage Shift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current display devices face challenges in achieving improved display quality due to parasitic capacitors affecting the voltage of sub-pixels, leading to suboptimal light emission and image quality.
Innovation Solution
The display device incorporates a semiconductor pattern, capacitor electrodes, and pixel electrodes configured to form transistors and capacitors, with a bridge electrode and insulating layers to maximize capacitance and minimize parasitic effects, ensuring accurate light emission and enhanced image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor configurations are used in display devices, then device complexity is reduced, but parasitic capacitors affect the voltage of sub-pixels, leading to degraded display quality and suboptimal light emission
Solution Approach 1:
The storage capacitor is divided into two separate capacitors: a first capacitor with a first capacitor electrode and a second capacitor with a second capacitor electrode. This segmentation allows each capacitor to be independently configured to minimize parasitic effects while maintaining the required total capacitance, thereby improving display quality without excessive complexity increase.
Solution Approach 2:
The capacitor electrodes are positioned at different vertical layers within the pixel structure. The first capacitor electrode is positioned at a first vertical position while the second capacitor electrode is positioned at a second vertical position, creating a multi-layered capacitor configuration that reduces parasitic coupling between adjacent sub-pixel components while maximizing storage capacitance.
2Quantity of substance
If capacitor electrodes are positioned to maximize capacitance, then storage capacitance is maximized, but parasitic capacitors still affect sub-pixel voltage and light emission
Solution Approach 1:
Each capacitor electrode is locally optimized in position and configuration. The first capacitor electrode is positioned at a first vertical position while the second capacitor electrode is positioned at a second vertical position, with each electrode having specific dimensional characteristics tailored to maximize its contribution to storage capacitance while minimizing parasitic effects in its local region.
Solution Approach 2:
The patent acknowledges the presence of parasitic capacitors but converts this potential harm into benefit by strategically positioning the first and second capacitor electrodes at different vertical positions. This configuration allows the parasitic capacitances to be minimized or utilized in a controlled manner, transforming what would be harmful voltage fluctuations into stable sub-pixel voltage control that enhances light emission consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively mitigates the influence of parasitic capacitors, allowing for precise light emission and improved display quality by maximizing the capacitance of storage capacitors, resulting in enhanced image display.
Implementation Method 1
A first capacitor may be formed by the first capacitor electrode and the second capacitor electrode
Implementation Method 2
A second capacitor may be formed by the second capacitor electrode and the first electrode that overlaps the second capacitor electrode
Implementation Method 3
The semiconductor pattern and the gate electrode may form a transistor
Data Source
AI summary
A display device includes a semiconductor pattern. A first capacitor electrode under the semiconductor pattern. A second capacitor electrode on the semiconductor pattern, the second capacitor electrode including a portion forming a gate electrode. A first electrode and a second electrode at a same layer on the second capacitor electrode. At least one light emitting element between the first electrode and the second electrode. A first pixel electrode on the first electrode and connected to a first end of the at least one light emitting element. A second pixel electrode on the second electrode and connected to a second end of the at least one light emitting element. The first electrode is connected to the first capacitor electrode and the semiconductor pattern. The semiconductor pattern and the gate electrode form a transistor. A first capacitor is formed by the first and second capacitor electrodes.