Sub-pixel Circuit for HMD Displays Managing Power and Voltage
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Solution Overview
Problem
Existing display technologies face challenges in achieving high-resolution panels for head-mounted display devices, particularly in managing power consumption and voltage fluctuations in sub-pixels, which affect the luminance and efficiency of light-emitting elements.
Innovation Solution
A sub-pixel design incorporating specific transistor and capacitor configurations, including P-type and N-type transistors, and capacitors with equal capacitances, to manage voltage levels and reduce power consumption by offsetting voltage changes during different operational periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sub-pixel designs are used in high-resolution panels, then resolution can be achieved, but power consumption increases and voltage fluctuations affect luminance stability
Solution Approach 1:
The gate line is divided into multiple sub-gate lines (first sub-gate line, second sub-gate line, etc.), and the transistor gate is correspondingly segmented. This segmentation allows independent control of different transistor groups, enabling precise timing control of data writing and emission operations, which reduces unnecessary power consumption while maintaining high-resolution display capabilities
Solution Approach 2:
The patent implements dynamic voltage compensation through capacitors (first capacitor, second capacitor, third capacitor) that actively adjust voltage levels during different operation periods. The emission control signal dynamically switches the third transistor between conductive and non-conductive states, allowing real-time adaptation of voltage levels to maintain stable luminance while reducing power consumption
2Device complexity
If conventional transistor configurations are used, then device simplicity is maintained, but voltage fluctuations occur during operation affecting luminance control
Solution Approach 1:
Capacitors are introduced as intermediary elements to store and regulate voltage levels. The first capacitor stores voltage for the first transistor, the second capacitor stores voltage for the fourth transistor, and the third capacitor compensates for voltage changes at the light emitting element. These intermediaries smooth out voltage fluctuations without significantly increasing device complexity
Solution Approach 2:
Capacitors pre-charge to appropriate voltage levels before emission periods, and the emission control signal prepares the third transistor by turning it on during data writing periods. This preliminary action ensures that voltage levels are already stabilized when emission begins, preventing luminance fluctuations while maintaining a relatively simple device structure
3Speed
If data writing and emission occur simultaneously, then operation speed is maintained, but voltage changes cause luminance fluctuations
Solution Approach 1:
The patent implements periodic action by dividing operation into distinct periods: data writing periods (when emission control signal is first level, third transistor conductive) and emission periods (when emission control signal is second level, third transistor non-conductive). This periodic separation ensures data is written and stored before emission occurs, eliminating voltage-induced luminance fluctuations while maintaining high operation speed through efficient timing
Solution Approach 2:
Data is written to the first and fourth transistors during data writing periods before the emission period begins. The capacitors store the voltage information in advance, so when the emission period starts and the third transistor turns off, the luminance is immediately and stably established without waiting for voltage stabilization, thus maintaining high operation speed while ensuring luminance stability
Data Source
AI summary
A sub-pixel includes a first transistor including a first electrode connected to a third node, a second electrode connected to a first node, and a gate electrode connected to a second node, a second transistor including a first electrode connected to the second node, a second electrode electrically connected to one of a plurality of data lines, and a gate electrode electrically connected to a first sub-gate line, a fourth transistor including a first electrode electrically connected to a third power line, a second electrode connected to the third node, and a gate electrode electrically connected to a second sub-gate line, a third capacitor including an electrode connected to the gate electrode of the fourth transistor and another electrode connected to the second node, and a fourth capacitor including an electrode connected to the gate electrode of the second transistor and another electrode connected to the second node.