Sub-Pixel Circuit Layout for Stable Grayscale in High-Resolution Displays
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Solution Overview
Problem
Existing display technologies face challenges in securing a sufficient voltage range for data signals, which affects the stability of grayscale implementation, particularly in high-resolution panels.
Innovation Solution
A sub-pixel design utilizing four transistors and three capacitors, including P-type and N-type transistors, with specific voltage control mechanisms to stabilize grayscale representation, allowing for high-resolution panel applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sub-pixel designs are used, then device complexity is reduced, but voltage range for data signals is insufficient affecting grayscale stability
Solution Approach 1:
The sub-pixel circuit is segmented into multiple functional blocks: a first transistor for driving the light emitting element, a second transistor for controlling data signals, a third transistor for emission control, and multiple capacitors (first, second, third capacitors) for voltage storage and regulation. Each component has a specific function in maintaining voltage ranges and grayscale stability, allowing the complex circuit to be managed through modular functional segmentation.
Solution Approach 2:
The invention utilizes parameter changes in transistor switching states and capacitor charging/discharging cycles to dynamically adjust voltage levels. The first transistor's source voltage varies between a first voltage and a second voltage, while capacitors store and release energy to maintain stable voltage ranges. This dynamic parameter adjustment enables sufficient voltage swing for data signals while maintaining grayscale stability.
2Reliability
If more transistors and capacitors are added to stabilize voltage range, then grayscale implementation becomes more reliable, but device complexity increases
Solution Approach 1:
The third transistor serves multiple functions: it controls the emission timing of the light emitting element and also regulates the voltage supplied to the first transistor's source. The capacitors perform dual roles of storing voltage for grayscale representation and filtering voltage fluctuations. This multi-functionality reduces the need for additional dedicated components, balancing reliability improvement with device complexity management.
Solution Approach 2:
The capacitors are pre-charged to specific voltage levels during non-emission periods to prepare the circuit for the next emission cycle. The first transistor's source voltage is pre-adjusted between the first and second voltages based on anticipated data signal requirements. This preliminary action ensures that voltage ranges are already optimized when data signals arrive, improving reliability without requiring complex real-time adjustment mechanisms.
3Manufacturing precision
If voltage control mechanisms are enhanced, then grayscale representation becomes more stable, but manufacturing complexity increases
Solution Approach 1:
The circuit employs self-regulating mechanisms where the capacitors automatically charge and discharge based on the switching states of the transistors, maintaining voltage stability without external intervention. The first transistor inherently regulates its source voltage between the first and second voltages through its switching operation, and the feedback from capacitor voltage levels automatically adjusts the circuit operation. This self-service capability simplifies manufacturing by reducing the need for complex external voltage regulation circuits.
Data Source
AI summary
A sub-pixel includes: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node configured to receive an initialization voltage and the third node; and a third capacitor connected between the third node and the second node.