Sub-Pixel Drive Circuit Layout Without Display Demultiplexers

The patent merges the functions of multiple demultiplexers into a single integrated circuit. The integrated circuit includes multiple scan signal generators that share common data input lines, allowing data voltages to be supplied to multiple sub-pixels through shared pathways. This consolidation reduces the total number of separate demultiplexer components while maintaining the ability to independently control each sub-pixel through the integrated logic.

The integrated circuit performs multiple functions within a single device: it generates scan signals for multiple sub-pixels, multiplexes data inputs, and distributes data voltages to appropriate sub-pixels based on scan signal timing. This multi-functional approach eliminates the need for separate dedicated demultiplexer circuits for each sub-pixel, reducing overall device complexity while preserving precise control capabilities.

By merging multiple demultiplexer functions into a single integrated circuit, the patent reduces the total power consumption. The integrated circuit can share power supply lines, control logic, and timing circuits across multiple sub-pixels, eliminating redundant power consumption that would occur in separate demultiplexer circuits. The scan signal generators within the integrated circuit are designed to operate efficiently by coordinating their output timing.

The integrated circuit uses periodic scan signals to sequentially select and supply data voltages to different sub-pixels. This periodic scanning approach allows the circuit to reuse the same data input lines and control logic for multiple sub-pixels over time, reducing the need for continuous power consumption that would be required if each sub-pixel had its own dedicated demultiplexer operating simultaneously.

The integrated circuit is segmented into multiple independent scan signal generators, each capable of controlling a specific sub-pixel. This segmentation allows the complex task of controlling high-resolution displays to be divided into manageable functional units within the integrated circuit, where each generator handles a portion of the overall pixel control while sharing common resources.

The patent transitions from a planar arrangement of separate demultiplexer circuits to a hierarchical integrated structure where multiple scan signal generators operate in parallel within a unified control architecture. This dimensional reorganization allows the system to handle high-resolution pixel control by adding functional complexity in the time domain through parallel scan signal generation, rather than increasing spatial complexity with separate circuits.