Sub-Pixel Circuit With Split Gate Lows for Accurate Black Grayscale

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Solution Overview

Problem

Existing display devices, particularly head-mounted displays, require high-resolution panels that are not adequately supported by current sub-pixel technologies, especially in implementing virtual and augmented reality applications.

Innovation Solution

A sub-pixel design incorporating specific transistor configurations and voltage levels, including a metal-oxide-semiconductor field-effect transistor (MOSFET) with distinct logic low levels for sub-gate signals and an initialization voltage, along with capacitors, to enhance black grayscale expression and improve operational reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional sub-pixel design is used, then the display device can operate with standard resolution, but it cannot adequately support high-resolution panels required for virtual and augmented reality applications

Engineering Contradiction:
ImproveresolutionVSAvoidoperational reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by using distinct logic low levels for different sub-gate signals (first sub-gate signal and second sub-gate signal have different logic low levels). This voltage differentiation enables precise control of multiple transistors in the sub-pixel circuit, allowing accurate grayscale expression and improved operational reliability for high-resolution display requirements in VR/AR applications

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the logic low level of the first sub-gate signal is the same as the logic low level of the second sub-gate signal, then the circuit design is simplified, but the black grayscale expression is inaccurate

Engineering Contradiction:
Improvegrayscale expression accuracyVSAvoidsignal voltage configuration
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different logic low levels to different sub-gate signals based on their specific functions. The first sub-gate signal and second sub-gate signal have differentiated logic low levels to precisely control different transistors (second transistor and fourth transistor respectively), enabling accurate local control for black grayscale expression while maintaining overall circuit functionality

Inventive Principle:
Principle #3Local quality

3Reliability

If the initialization voltage is set to a high level, then the transistor initialization is robust, but it conflicts with the logic low level of the second sub-gate signal

Engineering Contradiction:
Improvetransistor initialization reliabilityVSAvoidvoltage level compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent resolves the voltage conflict by applying parameter changes - specifically setting the logic low level of the second sub-gate signal to be lower than the initialization voltage, while maintaining the logic high level at a higher voltage. This voltage parameter differentiation ensures both reliable transistor initialization and proper signal control functionality without conflict

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250384823A1Sub-pixel, display device including the same, and electronic device including the same
Publication Date: 2025.12.18 SAMSUNG DISPLAY CO LTD
  • US20250384823A1 patent drawing
  • US20250384823A1 patent drawing
  • US20250384823A1 patent drawing

AI summary

A sub-pixel includes a first transistor connected between a first power voltage node and a first node, and including a gate terminal connected to a second node, a second transistor connected between the second node and a data line, and including a gate terminal connected to a first sub-gate line, a fourth transistor connected between the first node and an initialization voltage node, and including a gate terminal connected to a second sub-gate line, and a light-emitting element connected between the first node and a second power voltage node, wherein a logic low level of a first sub-gate signal configured to be received by the first sub-gate line is different from a logic low level of a second sub-gate signal configured to be received by the second sub-gate line.