Sub-Pixel Initialization Line Layout for High-Resolution Displays
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Solution Overview
Problem
The increase in sub-pixel size and decrease in the number of sub-pixels due to the need for two contact areas to receive initialization voltages from separate power lines, leading to a decrease in display device resolution.
Innovation Solution
A display device design with alternating first and second power lines and transmission lines, allowing each sub-pixel to receive initialization voltages through a single power line, reducing the size of each sub-pixel and increasing the number of sub-pixels per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate power lines are provided to each sub-pixel to deliver first and second initialization voltages, then the initialization function is achieved, but the sub-pixel size increases and the number of sub-pixels per unit area decreases
Solution Approach 1:
The patent merges the functions of first and second power lines by having them share a common physical line. The first power line delivers both first initialization voltage (to gate electrode) and second initialization voltage (to light emitting diode) through different time periods, while the second power line delivers emission voltage. This consolidation reduces the number of separate lines needed per sub-pixel, thereby reducing sub-pixel size and increasing the number of sub-pixels that can be accommodated in a given display area.
2Reliability
If two contact areas are provided in each sub-pixel to receive initialization voltages from separate power lines, then the initialization function is achieved, but the sub-pixel area increases and resolution decreases
Solution Approach 1:
The patent consolidates the contact structure by providing only one contact area per sub-pixel. This single contact area receives both first initialization voltage and second initialization voltage through the first power line at different time periods, eliminating the need for two separate contact areas. This reduction in contact area directly reduces the overall sub-pixel area, enabling higher resolution displays with more sub-pixels per unit area.
Solution Approach 2:
The patent employs periodic action by delivering different voltages through the same power line at different time periods. The first power line delivers first initialization voltage during a first time period and second initialization voltage during a second time period. This time-division multiplexing approach allows a single contact area to serve multiple initialization functions, reducing the spatial requirements of each sub-pixel.
3Reliability
If separate first and second power lines are disposed in each row, then initialization voltages can be delivered, but the line density increases and manufacturing defects increase
Solution Approach 1:
The patent merges the first power line and second power line into a single shared power line structure. Instead of providing separate first and second power lines in each row, the first power line is shared to deliver both first initialization voltage and second initialization voltage at different time periods. This merging reduces the overall line density in the display device, simplifying the wiring structure and reducing manufacturing complexity and potential defects.
4Reliability
If separate first and second power lines are provided, then initialization voltages can be delivered, but the capacitance-induced resistance increases and scan-on time is insufficient
Solution Approach 1:
The patent merges the power line structure to reduce total capacitance. By consolidating the first and second power lines into a shared first power line, the total capacitance in the system is reduced, which in turn reduces capacitance-induced resistance. This improvement allows sufficient scan-on time to be achieved, ensuring proper initialization and operation of the sub-pixels without time constraints.
Data Source
AI summary
A display device includes a substrate including sub-pixel circuit areas that are arranged in m rows and n columns, where m and n are positive integers, first gate lines extending in a row direction, data lines extending in a column direction, initialization power lines extending in the row direction, including first power lines disposed in sub-pixel circuit areas of odd rows and receiving a first initialization voltage and second power lines disposed in sub-pixel circuit areas of even rows and receiving a second initialization voltage, and transmission lines extending in the column direction, including first transmission lines disposed in sub-pixel circuit areas of odd columns and receiving the first initialization voltage from the first power lines and second transmission lines disposed in sub-pixel circuit areas of even columns and receiving the second initialization voltage from the second power lines.