Sub-Pixel Column Layout for Faster Data Charging in Displays
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Solution Overview
Problem
Display devices face issues with incomplete data charging in sub-pixels due to increased driving frequency, leading to reduced charging rates and potential luminance deviations and screen abnormalities.
Innovation Solution
Incorporation of a sensing transistor to sense the characteristic values of sub-pixels, allowing for improved data voltage charging rates and compensation, along with a novel arrangement of sub-pixels and data lines to reduce RC delay and expand the light-emitting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the driving frequency is increased to smoothly drive the display panel, then the display refresh rate is improved, but the charging time of data voltage in sub-pixels is reduced leading to incomplete charging
Solution Approach 1:
The patent applies preliminary action by performing data voltage charging in two stages: a first charging period during the normal display period, and a second charging period during the blanking period before the next frame. This allows the sub-pixel to complete its charging even when the driving frequency is increased, as the charging process starts in advance and continues into the blanking period when the pixel is not being displayed.
2Productivity
If the driving frequency is increased, then the display refresh rate is improved, but data cannot be completely charged in the sub-pixel leading to luminance deviations
Solution Approach 1:
The patent extends the data voltage charging process into the blanking period before the next frame is displayed. This preliminary charging action ensures that even at high driving frequencies, the sub-pixel receives sufficient charge to maintain accurate luminance levels, preventing the luminance deviations and screen abnormalities that would otherwise occur.
3Device complexity
If sub-pixels are arranged in conventional patterns, then the pixel structure is simple, but the charging rate of data voltage is reduced due to RC delay
Solution Approach 1:
The patent changes the spatial arrangement of sub-pixels from conventional patterns to a specific sequential disposition along the same column (e.g., R-G-B-W order vertically). This dimensional reorganization reduces the RC delay in data line connections and improves the charging rate of data voltage without significantly increasing structural complexity.
Data Source
AI summary
A display device according to an exemplary embodiment of the present disclosure includes a display panel in which a plurality of pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel that have different colors are disposed; a data driver configured to supply data voltages to the plurality of pixels through a plurality of data lines; and a gate driver configured to supply gate signals to the plurality of pixels through a plurality of gate lines; wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially disposed in the same column, so that it is possible to improve a charging rate of a data voltage.