Video Compression Co-Processor for Subpixel Motion Estimation
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Solution Overview
Problem
Current video data compression techniques, particularly motion estimation, are computationally intensive and costly to implement, even when using powerful processing capabilities of field-programmable object arrays (FPOAs), and they often result in less than ideal operating performance.
Innovation Solution
An integrated circuit with a video compression co-processor integrated within a programmable integrated circuit, featuring a configurable array of elements, including a search engine and a subpixel engine, which calculates the sum of absolute differences and interpolates subpixels to efficiently perform motion estimation, thereby offloading video data compression tasks and optimizing processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If motion estimation is implemented using FPOA, then video compression capability is provided, but processing performance and compression quality remain less than ideal
Solution Approach 1:
The patent divides the video compression system into two distinct segments: a configurable array of programmable objects for general-purpose processing and a dedicated video compression co-processor for specialized motion estimation tasks. This segmentation allows each component to be optimized for its specific function, with the co-processor handling computationally intensive compression operations while the FPOA handles other processing needs.
Solution Approach 2:
The video compression co-processor acts as an intermediary component between the FPOA and external memory systems. It receives pixel data from memory, performs specialized compression algorithms, and returns results to the FPOA, thereby offloading complex compression calculations from the general-purpose array and improving overall processing performance.
2Productivity
If video compression processing is performed, then data compression is achieved, but design complexity increases
Solution Approach 1:
The patent extracts the complex video compression functionality from the main FPOA architecture and places it in a separate, dedicated co-processor unit. This extraction removes the complexity of implementing compression algorithms from the core array design, allowing the FPOA to remain a clean, configurable platform while the co-processor handles the specialized compression tasks.
Solution Approach 2:
The video compression co-processor is designed with universal interfaces that allow it to work with the FPOA for various compression standards and applications. The co-processor can be configured to handle different video formats and compression algorithms, providing multi-functional capability that reduces overall system design complexity while maintaining high compression performance.
Data Source
AI summary
A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.