Sub-Pixel S-Factor Layout for Low-Gray Mura Reduction

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Solution Overview

Problem

Existing display devices face issues with mura defects at low gray scale values due to differences in operating characteristics of light emitting elements for different colors, leading to unevenness in voltage ranges across sub-pixels.

Innovation Solution

The display device optimizes the S-factor for each sub-pixel by adjusting the distance between the active layer and the metal layer, applying a high S-factor to red and green sub-pixels and a low S-factor to the blue sub-pixel to ensure appropriate voltage ranges and reduce mura.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a high S-factor is applied to all sub-pixels, then the range of data voltages for expressing gray scale increases for red and green sub-pixels, but the blue sub-pixel exceeds the voltage specification of the data driver

Engineering Contradiction:
Improvegray scale expression rangeVSAvoidvoltage specification compliance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies different S-factor values to different sub-pixel types (red, green, blue) based on their individual light emitting element efficiencies. Specifically, the blue sub-pixel uses a lower S-factor (0.6-0.8) while red and green sub-pixels use higher S-factors (0.8-1.0), allowing each sub-pixel to operate within its optimal voltage range and comply with data driver specifications.

Inventive Principle:
Principle #3Local quality

2Reliability

If a low S-factor is applied to all sub-pixels, then the blue sub-pixel maintains appropriate voltage range, but the red and green sub-pixels have excessively narrow voltage ranges causing mura at low gray scale

Engineering Contradiction:
Improvevoltage specification complianceVSAvoidgray scale expression range
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements sub-pixel-specific S-factor optimization where red and green sub-pixels receive higher S-factor values (0.8-1.0) to ensure adequate gray scale expression range, while the blue sub-pixel receives a lower S-factor (0.6-0.8) to maintain voltage compliance. This localized differentiation eliminates mura defects in red and green sub-pixels while preventing voltage specification violations in blue sub-pixels.

Inventive Principle:
Principle #3Local quality

3Device complexity

If the same S-factor is applied to all sub-pixels, then the structure is simple, but mura defects occur in specific sub-pixels due to different light emitting element efficiencies

Engineering Contradiction:
ImproveS-factor configurationVSAvoiddisplay uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent differentiates S-factor configuration by sub-pixel type (red, green, blue) to match their respective light emitting element efficiencies. This approach increases structural complexity slightly but significantly improves display uniformity by preventing mura defects in specific sub-pixels, making the quality improvement worth the added complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12219815B2Display device
Publication Date: 2025.02.04 LG DISPLAY CO LTD
  • US12219815B2 patent drawing
  • US12219815B2 patent drawing
  • US12219815B2 patent drawing

AI summary

A display device can include a plurality of sub-pixels disposed on a substrate; a storage capacitor disposed in each of the plurality of sub-pixels; a buffer layer disposed on the storage capacitor; a transistor disposed on the buffer layer in each of the plurality of sub-pixels; and a light emitting element disposed on the transistor in each the plurality of sub-pixels, in which the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of the first, second and third sub-pixels being configured to emit a different color of light, at least one of the plurality of sub-pixels includes a metal layer disposed below the transistor, and the metal layer is connected to one electrode of the storage capacitor.