Sub-Pixel Transistor Layout With Under-Stacked Storage Capacitor
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Solution Overview
Problem
Designing a high-resolution display panel with a high aperture ratio for sub-pixels is challenging due to the fixed number and type of elements, such as transistors and storage capacitors, which limits the ability to increase the aperture ratio.
Innovation Solution
A display device structure is implemented with a bottom gate driving transistor and a storage capacitor formed below the transistor, along with a unique connection between the source electrode and pixel electrode, to enhance the aperture ratio by optimizing the layout and configuration of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number and type of elements (transistors, storage capacitors, light-emitting elements) in each sub-pixel are fixed, then the sub-pixel structure is simplified, but the aperture ratio cannot be increased
Solution Approach 1:
The patent merges the storage capacitor and driving transistor into a single integrated structure where the storage capacitor is formed below the driving transistor. The first capacitor electrode is electrically connected to the source electrode, and the second capacitor electrode overlaps with the gate electrode, combining multiple functions into one compact unit that increases the aperture ratio while maintaining necessary circuit functions.
Solution Approach 2:
The patent utilizes vertical stacking to arrange components in multiple layers. The storage capacitor is positioned in a lower layer while the driving transistor is in an upper layer, with the active layer extending through both layers. This three-dimensional arrangement allows efficient space utilization and increases the aperture ratio without adding more planar elements.
2Area of moving object
If the aperture ratio of sub-pixel is increased, then the resolution of display panel is improved, but the circuit part length of driving transistor increases
Solution Approach 1:
The patent moves the storage capacitor to a lower layer vertically beneath the driving transistor, utilizing the third dimension (vertical stacking) rather than expanding horizontally. This reduces the planar footprint and circuit part length while maintaining the aperture ratio, as components are arranged in layers rather than spreading out in the plane.
Solution Approach 2:
The storage capacitor is nested within the area occupied by the driving transistor. The first capacitor electrode is connected to the source electrode, and the second capacitor electrode overlaps with the gate electrode, allowing the capacitor to be contained within the transistor's footprint. This nesting arrangement minimizes the overall circuit part length while maintaining both functions.
3Area of moving object
If the aperture ratio is increased by optimizing component layout, then the resolution is improved, but the manufacturing complexity increases
Solution Approach 1:
The integrated structure of the storage capacitor and driving transistor allows both components to be formed using the same thin-film deposition and patterning processes. The active layer is formed continuously through both the capacitor and transistor regions, and electrodes are patterned in a unified sequence, simplifying manufacturing despite the optimized layout.
Solution Approach 2:
The patent segments the device into distinct functional layers: the storage capacitor region with first and second capacitor electrodes, the driving transistor region with active layer and gate electrode, and the light-emitting region with pixel electrode. This segmentation allows each component to be manufactured using standard thin-film processes while maintaining the optimized integrated layout for high aperture ratio.
Data Source
AI summary
Embodiments of the present disclosure relate to a transistor and a display device, and more particularly, to a display device including a substrate, a first capacitor electrode on the substrate, a first buffer layer on the first capacitor electrode, a second capacitor electrode located on the first buffer layer and overlapping at least a portion of the first capacitor electrode, a second buffer layer on the second capacitor electrode, an active layer on the second buffer layer, a gate insulating film on the active layer, and a source electrode located on the gate insulating film and overlapping at least a portion of the active layer, and the active layer overlaps at least a portion of an overlapping region between the first capacitor electrode and the second capacitor electrode to provide a sub-pixel having a high aperture ratio structure, thereby providing a high-resolution image.