Sub-Pixel Circuit Layout With Adjacent Transistor Channels
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Solution Overview
Problem
Existing display devices, particularly Head-Mounted Displays (HMDs), require high-resolution panels that necessitate advanced pixel designs to achieve optimal performance in Virtual Reality (VR) or Augmented Reality (AR) applications.
Innovation Solution
A display device with a pixel configuration that includes first, second, and third sub-pixels, each with a sub-pixel circuit and light-emitting element, where transistors performing similar functions are arranged in adjacent channels, with specific gate and data signal connections to enhance pixel efficiency and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors in sub-pixel circuits are arranged in adjacent channels, then manufacturing precision and resolution are improved, but device complexity increases
Solution Approach 1:
The pixel circuit is divided into multiple sub-pixel circuits (first, second, third sub-pixel circuits), each with its own transistors arranged in adjacent channels. This segmentation allows for precise control of each sub-pixel while maintaining organized connectivity patterns that reduce overall device complexity.
Solution Approach 2:
Transistors performing the same function across different sub-pixel circuits are merged into adjacent channels (e.g., first transistors in first, second, and third sub-pixel circuits are arranged in adjacent channels). This merging strategy improves manufacturing precision by creating uniform, repeatable patterns while reducing the complexity of interconnections through spatial organization.
2Measurement precision
If high resolution panel is applied to HMD, then display quality is improved, but pixel design complexity increases
Solution Approach 1:
Each sub-pixel circuit is designed with specific local characteristics - the first, second, and third sub-pixel circuits have transistors arranged in adjacent channels with optimized connectivity. This local quality approach allows high resolution to be achieved through precise local transistor arrangements rather than complex global design.
Solution Approach 2:
The patent transitions from conventional two-dimensional pixel layouts to a three-dimensional channel arrangement where transistors are positioned in adjacent channels. This dimensional change enables higher resolution by utilizing vertical channel stacking, reducing the horizontal space required for each pixel while maintaining circuit functionality.
3Reliability
If multiple sub-pixel circuits are integrated in a pixel, then display performance is improved, but area occupied increases
Solution Approach 1:
Multiple sub-pixel circuits are nested within a single pixel structure, with first, second, and third sub-pixel circuits integrated in the same pixel. The transistors of these nested circuits are arranged in adjacent channels, allowing compact packaging that reduces the overall pixel area while maintaining the performance benefits of multiple sub-pixel circuits.
Data Source
AI summary
A display device includes a first sub-pixel including a first sub-pixel circuit, and a first light-emitting element configured to emit light based on a first data signal, a second sub-pixel including a second sub-pixel circuit, and a second light-emitting element configured to emit light based on a second data signal, and a third sub-pixel including a third sub-pixel circuit, and a third light-emitting element configured to emit light based on a third data signal, wherein channels of transistors configured to perform a same function among transistors in the first, second, and third sub-pixel circuits are adjacent to each other.