Sub-Pixel Circuit Layout for High-PPI Voltage Compensation
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Solution Overview
Problem
Display devices face challenges in integrating components with minimal width to meet design rules in a small surface area, particularly in achieving low surface area and high pixels per inch (ppi) for virtual and augmented reality applications, leading to limitations in minimizing transistors within sub-pixels.
Innovation Solution
A sub-pixel design incorporating multiple transistors and capacitors to manage voltage distribution, including a first transistor for generating driving current, capacitors for voltage storage, and additional transistors for providing data and reference voltages, along with a light-emitting element, to optimize voltage application and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If components are integrated in minimized surface area to achieve low surface area and high ppi, then display density is improved, but transistor integration is limited due to minimum width requirements
Solution Approach 1:
The sub-pixel circuit is divided into multiple functional blocks: a first transistor for generating driving current, a second transistor for providing data voltage, a third transistor for providing reference voltage, and capacitors for voltage storage. This segmentation allows each component to be optimized independently while maintaining overall integration density.
Solution Approach 2:
The patent employs multi-layer stacking of transistors and capacitors in the vertical dimension to achieve three-dimensional integration. By stacking components vertically rather than only horizontally, the circuit achieves higher integration density without increasing the planar footprint, thus resolving the contradiction between high pixel density and transistor integration complexity.
2Reliability
If multiple transistors and capacitors are added to manage voltage distribution, then voltage control is improved, but device area increases
Solution Approach 1:
Multiple transistors and capacitors are merged into a single integrated sub-pixel structure with shared wiring. The first, second, and third transistors along with capacitors C1 and C2 are combined in a compact arrangement where common nodes are shared, reducing the overall area while maintaining proper voltage distribution control.
Solution Approach 2:
The capacitors C1 and C2 serve multiple functions: storing data voltage, storing reference voltage, and providing voltage compensation. The transistors are configured to perform both voltage generation and voltage regulation functions, reducing the need for separate dedicated components and thereby minimizing the sub-pixel area.
3Use of energy by stationary object
If data voltage is written unaltered, then power consumption is reduced, but voltage distribution control becomes more difficult
Solution Approach 1:
The circuit incorporates feedback through the third transistor and capacitor C2, which store reference voltage and provide compensation for threshold voltage shifts. This feedback mechanism allows the system to maintain stable voltage distribution even when writing unaltered data voltages, reducing power consumption while controlling voltage distribution through automatic compensation rather than active regulation.
Data Source
AI summary
A sub-pixel may include a first transistor configured to generate a driving current, a first capacitor including a first electrode connected to a first electrode of the first transistor, and a second electrode, a second capacitor including a first electrode connected to a control electrode of the first transistor, and a second electrode connected to the second electrode of the first capacitor, a second transistor configured to provide a data voltage to the second electrode of the first capacitor in response to a write gate signal, and a light emitting element configured to receive the driving current and emit light.